MLK-15351: PCI: imx: Only use pcie_bus_regulator for iMX6QP
The pcie_bus_regulator is only used by the iMX6QP board,
so only request the regulator for this variant.
Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com>
MLK15034: ARM: cpuidle imx7d: Declare longer exit_latency/target_residency
Low power idle exit latency is much longer than declared, in the
milisecond range.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
MLK15034: ARM: cpuidle imx7d: Use a single counter for lpi flow
The current code for deciding which CPU runs the complete lpi flow is
too complicated. Since all enter/exit code now runs under the same lock
we can just use a single non-atomic counter of cpus inside lpi.
Another variable is used to make num_online_cpus() available to ASM code
but idle code can treat it as a constant.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
MLK15034: ARM: cpuidle imx7d: Check IPIs manually before LPI
The GPC will wake us on peripheral interrupts but not IPIs. So check
them manually by reading the GIC's GICD_SPENDSGIR* registers and
aborting idle if something is pending.
We do this only for the last cpu and after taking the required locks.
We know that at this stage the other cpu is in WFI itself or waiting for
the imx_pen_lock and can't trigger any additional IPIs. This means that
the check is not racy.
This fixes occasional ...
MLK15034: ARM: cpuidle imx7d: Extend imx_pen lock to cover entire flow
This makes the code much easier to reason about. In particular it o
makes sure the imx7d cpuidle driver respects the requirements for
cpu_cluster_pm_enter/exit:
* cpu_cluster_pm_enter must be called after cpu_pm_enter has been called
on all cpus in the power domain, and before cpu_pm_exit has been called
on any cpu in the power domain.
* cpu_cluster_pm_exit must be called after cpu_pm_enter has been called
on all cpus in...
MLK-15347 clk: imx: correct sccg and frac pll rate calculation error
- For SCCG SCCG_PLL2 type, its parent rate is with round-up,
using parent rate to calculate its rate will introduce
some error, like below sys1_pll2, its rate is actually 800M,
but we got 800000004:
sys1_pll1_ref_sel 1 1 25000000 0 0
sys1_pll1_ref_div 1 1 25000000 0 0
sys1_pll1 1 1 1600000000 0 0
sys1_pll1_out 1 1 1600000000 0 0
...
MGS-3021-2 [#imx-622] Disable GPU security feature to align VSI
revert the former patch which disabled GPU security feature.
revert the former patch which disabled GPU security feature.
rework on this patch as VSI suggested.
GPU security feature is only for mscale, but driver is not ready,
need disable this feature to avoid gpu kernel panic temporally,
will drop this patch when gpu security driver is ready later.
Date: 30th June, 2017
Signed-off-by: Chenyan Feng <ella.feng@nxp.com>
MLK-15319 imx8qm/imx8qx: Update to SCFW API based on commit:
"
commit a645f3c4c529e1f8cc5a624a047a3af56cfd39e1
Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Date: Thu Jun 29 15:21:53 2017 -0500
Turn off all HDMI-TX clocks by default. This is required for setting
the rate of the DIG PLL.
Add code to enable/disable the correct clocks before SECO accesses the HDMI SS.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
"
Signed-off-by: Ranjani Va...
MLK-15322-10 ARM64: dts: imx8mq-evk: connect mipi dsi to adv7535
Add port in dsi and adv7535 to connect them.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-15322-5 clk: imx: imx8mq: add ahb/ipg clocks for dsi
Add the ahb and ipg clocks for mipi dsi rxesc and txesc.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-15322-2 clk: imx: imx8mq: configure video_pll1 clock
Set the video_pll1 clock's source and rate which are
used for pixel clock and mipi dphy reference clock
source.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MA-9807: Fix ecb(aes) use without an IV
CAAM aes modes share descriptors, because of this CAAM requires an IV
for ECB. ECB does not need an IV and users do not have to pass valid
IV vectors. To allow correct usage with minimum impact to the driver a
zero IV is provided by the driver for ECB operations that need it.
Signed-off-by: Radu Solea <radu.solea@nxp.com>
MLK-15340-4: ARM64: dts: support SPDIF, MQS, SAI in imx8qm
Add two new dts for spdif and mqs, which are supported by
imx8qm validation board with debug base board. The spdif and
mqs use same output pin.
The connection in debug base board is:
WM8962:
CODEC_PWR_EN : SEAF_B_B7
CODEC_I2C_CLK: SEAF_B_J32
CODEC_I2C_DAT: SEAF_B_J31
AUD_MCLK : SEAF_B_H24
AUD_TXC : SEAF_B_B35
AUD_TXFS : SEAF_B_B36
AUD_TXD : SEAF_B_B37
AUD_RXD : SEAF_B_A36
HEADPHONE_DET...
MLK-15340-1: ASoC: wm8962: fix lambda value
According RM, the FLL_LAMBDA must be set to non-zero value in
integer and Franctional modes.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Mihai Serban <mihai.serban@nxp.com>
MLK-13945-3: ASoC: fsl_asrc: support two asrc devices
In imx8qm, there is two asrc devices, so using global structure
"miscdevice" will cause error. Each instance should have their
own structure.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-13945-2: ASoC: imx_mqs: specify clock name in machine driver
specify clock name in machine driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-13945-1: ASoC: fsl_mqs: refine the mqs driver for support imx8qm
IOMUXC_GPR2 register is not used for imx8, there is a new register
designed for this usage in imx8, so it also need the ipg clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-13947: ASoC: fsl_spdif: introduce SoC specific data
Introduce a SoC data struct which contains the differences between
the different SoCs this driver supports. This makes it easy to support
more differences without having to introduce a new switch/case each
time.
And in imx8qm, the spdif has two interrupt numbers and the burst size
should be 2 for EDMA limitation to support dual FIFO.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nx...
MLK-15342-3 cpufreq: add i.mx8mq support
Add i.MX8MQ cpufreq support, current version of
EVK board does NOT support voltage scale, but next
version will add this support, so this driver only
supports cpu frequency scale, voltage scale will
be added later once new board available.
A53 CPU clock normally is from ARM_PLL, but during
ARM_PLL relock window, it will be switched to
SYS1_PLL_800M to avoid clock missing, and after
arm pll relock done, it will be switched back.
Signed-off-by: Anson ...
MLK-15342-2 arm64: dts: freescale: imx8mq: add cpu opp table
Add i.MX8MQ cpu OPP table info for cpu-freq driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15342-1 soc: imx: i.mx8mq uses its own cpu-freq driver
i.MX8MQ is a SMP SoC without system controller, so
it will has its own cpu-freq driver, add machine
check for different platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15330-3 dma: fsl-edma-v3: add dual fifo support
There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
MLK-15330-2: ARM64: imx8qm/qxp: modify all device nodes using edmav3
Modify all device nodes which use edmav3,since dma-cell down from 4 to
3.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
MLK-15330-1: dma: fsl-edma-v3: combine two cells into one
For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
for user and it's possible other cells maybe added to other use cases,
so combine two cells into one now, and for some special use cases such as
dual fifo property can directly be passed by one bit of cell3 rather than
another cell.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
MLK-15333-02 driver: clk: need to check the ack bit of frac pll on imx8mq
On i.MX8MQ, when do frac pll's frequency, if the PLL is not powerdown & bypass,
we must do new_div_ack check after we reload the divff and divfi value,
otherwise, the frac pll will lock to a wrong freqeuncy sometimes.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15333-01 driver: clk: Fix clock round to a wrong rate issue
The divider 'CLK_DIVIDER_ROUND_CLOSEST' flag should be enabled,
otherwise, the round clock will return a wrong clock rate.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15149-01 driver: soc: add gpc power domain support on i.mx8mq
Add generic power domain driver support on i.mx8mq. The power
domain on/off operations need to use the SIP service call to
trap into secure monitor to handle it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15328-1 input: keyboard: add i.mx8mq snvs onoff button support
i.MX8MQ use SNVS ONOFF button, add support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15296-3: ASoc: fsl: remap the dsp firmware
In order to use the hifi4's Cache to cache the firmware's
.rodata, .text, .data, .bss section and hifi4 core lib's
.text section, the firmware's .rodata, .text, .data and
.bss section should be remaped to 0x20700000 - 0x20FFFFFF
address range. This patch is used to parse the firmware
and load each section to corresponding address range.
This patch also set csr_gpr_control to 0x515A2080 to
remap the hifi4's address range in SCFW.
In addtion, ad...
