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AuthorCommitMessageCommit Date
Weiguang KongWeiguang Kong
0bd5a48851dMLK-15296-2: include: uapi: add consumed cycles add a new structure element(cycles) to save the consumed cycles that returned from dsp framework Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
Richard ZhuRichard Zhu
6874e98c374MLK-15307-3 PCI: imx: add the imx8mq pcie Add the imx8mq pcie support Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Richard ZhuRichard Zhu
f5f9dcc68f2MLK-15307-2 clk: imx8mq: set the parent clocks of PCIE Configure the parent clocks of PCIE. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Richard ZhuRichard Zhu
0fd68669f72MLK-15307-1 ARM64: dts: imx: enable pcie on mscale There are two PCIE ports on mscale. This commit enable the pcie support on the mcsale EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Chenyan FengChenyan Feng
17350ff02aaMGS-3054 dts: update gpu shader clock to meet design changed gpu shader clock from 1G to 800Mhz per design also updated gpu shader parent from SYS2_PLL to SYS1_PLL.
Mihai SerbanMihai Serban
ff9b869bfb8MLK-15101: ASoC: imx-wm8962: Use a lower FLL output rate for S20_3LE and S24_LE formats Using a lower FLL out frequency seems to fix the sound distortion we hear during playback of the second audio file from the command: aplay -Dhw:0 -d 1 audio96k16b2c.wav audio96k24b2c.wav Because the new frequency is half of the old one the existing BLCK compute formula from wm8962 codec driver is still correct, it can derive the new FLL output frequency. Signed-off-by: Mihai Serban <mihai.serban@nxp.com...
Bai PingBai Ping
6d7712540c5MLK-15314 driver: clk: Change the audio ahb clock to sys2_pll_500m Change the audio ahb clock source to sys2_pll_500m clock. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Bai PingBai Ping
32d69633cc0MLK-15310 driver: clk: Correct post divider width of ip clock on i.mx8mq The post divider bits width of IP clock root should be 6, not 3 on i.MX8MQ, so correct this. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Fugang DuanFugang Duan
68d2e632a17MLK-15312 arm64: defconfig: enable 802.2 LLC Enable IEEE 802.2 LLC protocol. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Fugang DuanFugang Duan
0487a0a5678MLK-15311 net: fec: change the default rx copybreak value to maximum Set the default rx copybreak value to maximum that can improve the performance when SMMU is enabled. User can change the copybreak vaule in dynamically by ethtool. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Fugang DuanFugang Duan
e39bca373c3MLK-15309-03 arm64: defconfig: enable PHY AT803X Add PHY AT803X support. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Fugang DuanFugang Duan
4c6e8ae20ceMLK-15309-02 arm64: dts: imx8mq-evk: add the enet PHY led_act blinding workaround Add enet PHY AR8031 led_act blinding issue sw workaround. Adjust the PIN drive strength for the better timing. Set the PTP ref clock to 100Mhz. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Fugang DuanFugang Duan
1efdead7f31MLK-15309-01 net: phy: at803x: add EEE mode, 1.8V IO, led_act blinding workaround support SmartEEE feature is enabled in default, add interface for user to disable the feature for IEEE1588 high accurate convergence. The phy support 1.8v RGMII VDDIO voltage, add interface for user to enable VDDIO 1.8v support. When phy/RJ45 power supply is not stable, LED_ACT may be busy on blinding, add sw workaround to fix the issue. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao...
Fugang DuanFugang Duan
f8c87398d59MLK-15308 arm64: dts: imx8mq-evk: add post delay for BT modem i.MX8MQ evk board install Murata 1CX WIFI/BT module, 1CX Bluetooth requires the post delay after BT_REG power on. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Peng FanPeng Fan
0da9623529cMLK-15302 imx8mq: add wdog support Add wdog nodes in dtsi. Enable wdog1 for imx8mq evk board. Enable imx wdt in defconfig. Correct clock, offset 0x4550 is actually for wdog3. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Frank LiFrank Li
a7999435515MLK-15300-2 dts: i.MX8QXP: perf: add irq number Assigned irq nubmber for ddr perf counter Signed-off-by: Frank Li <Frank.Li@nxp.com>
Frank LiFrank Li
a9fd984d5baMLK-15300-1 perf: fixed crash when irq have not assigned in dts file [ 28.061044] perf[2494]: PC Alignment exception: pc=0000000072656d69 sp=ffff800032f2bd30 [ 28.069061] Internal error: Oops - SP/PC alignment exception: 8a000000 1 PREEMPT SMP [ 28.077066] Modules linked in: [ 28.080128] CPU: 2 PID: 2494 Comm: perf Not tainted 4.9.11-02540-g3ebe22c #52 [ 28.087263] Hardware name: Freescale i.MX8QXP LPDDR4 ARM2 (DT) [ 28.093093] task: ffff80002e097080 task.stack: ffff800032f28000 [ 28.099011]...
Robin GongRobin Gong
cb38feb099eMLK-15034: dma: imx-sdma: no need report interrupt for channel0 It is possible for an irq triggered by channel0 to be received later, after clks are disabled. If that happens then clearing them by writing to SDMA_H_INTR won't work and the system will hang processing infinite interrupts. Actually, don't need interrupt triggered on channel0 since it's pollling to know channel0 done rather than interrupt in current code, just clear BD setting to disable channel0 interrupt to avoid the above cas...
Octavian PurdilaOctavian Purdila
6545fccc1adMLK-15083 watchdog: imx2_wdt: fallback to timeout reset if explicit reset fails If explicit reset fails fallback using the watchdog timeout. We already have set the timeout counter to 0, but we might need to ping the watchdog to load the new timeout, if a previous watchdog timeout value has already been set. We also decrease the time we spend waiting, to give a chance to log that the explicit reset failed and that we fallback to watchdog timeout reset. Signed-off-by: Octavian Purdila <octa...
Peng FanPeng Fan
3b50c890b68MLK-15007-4: arm64: dts: imx8qm: enable iommu for fec Enable iommu for FEC1/2. The SID is programmed in U-BOOT with value 0x12 that shared by FEC/FEC2, so FEC1/2 will share one SID and one context. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng FanPeng Fan
4e9bab2f399MLK-15007-3 arm64: defconfig: enable SMMUv2 Enable SMMUv2 in defconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng FanPeng Fan
1e404ea0d64MLK-15007-2 arm64: dts: imx8qm: add smmu node Add smmu node for i.MX8QM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng FanPeng Fan
1d98cab5683MLK-15007-1 iommu: arm: pgtable: alloc pagetable in DMA area Normally the iommu pagetable could be in 64bit address space, but we have one patch to address PCIE driver, 'commit 9e03e5076269 ("MLK-15064-2 ARM64: DMA: limit the dma mask to be 32bit")' The patch restrict swiotlb and iommu dma to be in 32bit address. So if we allocate pages in highmem, then dma_map_single will return a 32bit address. Then, we will get "Cannot accommodate DMA translation for IOMMU page tables", because `dma != ...
Nipun GuptaNipun Gupta
949a37280b7iommu/arm-smmu: Set SMTNMB_TLBEN in ACR to enable caching of bypass entries The SMTNMB_TLBEN in the Auxiliary Configuration Register (ACR) provides an option to enable the updation of TLB in case of bypass transactions due to no stream match in the stream match table. This reduces the latencies of the subsequent transactions with the same stream-id which bypasses the SMMU. This provides a significant performance benefit for certain networking workloads. With this change substantial performa...
Han XuHan Xu
cb01adf04adMLK-15284-6: arm64: defconfig: enable UBIFS in defconfig enable ubifs in arm64 defconfig Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
0d2ee7307c9MLK-15284-5: arm64: defconfig: add GPMI and MXS_DMA in default config add GPMI_NAND and MXS_DMA in ARM64 default config Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
8bef30a5033MLK-15284-4: dma: Kconfig: add MXS_DMA dependency for ARM64 add MXS_DMA dependency for ARCH_MXC_ARM64 The patch also merge the upstreamed change that extend the dependency to allow the mxs dma driver to be built whenever ARCH_MXS or ARCH_MXC is selected. Refer to https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/drivers/dma/Kconfig?h=next-20170626&id=d762e4f35601239cbebfbfd43d99876d8f220927 Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
0d370845dbfMLK-15284-3: mtd: nand: gpmi-nand: support NAND on i.MX8QXP Enable the NAND support on i.MX8QXP Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
9cb9f08bbdfMLK-15284-2: dma: mxs-dma: add i.MX8QXP support in mxs-dma add one more entry for i.MX8QXP mxs-dma, also check mxs_dma in filter function. Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
33b07b53bb3MLK-15284-1: arm64: dts: enable the GPMI NAND module in device tree enable the GPMI NAND module in device tree for i.MX8QXP Signed-off-by: Han Xu <han.xu@nxp.com>
Leonard CrestezLeonard Crestez
dbb021dec43arm64: defconfig: Fix config option order Continuous integration complains if savedefconfig shows differences, even if it's just because of reordering config options. Fixes: 42929061c62b ("MGS-3025: ARM64: dts: freescale: imx8mq: enable viv drm") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Octavian Purdila <octavian.purdila@nxp.com>
Gao PanGao Pan
1c34b08e3c7MLK-15293 arm64: dts: imx8mq: add imx i2c support add imx i2c support for imx8mq in dts files. Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Bai PingBai Ping
ad11b8f6f3bMLK-15145 ARM64: dts: Correct the system counter freqency for i.mx8mq On i.MX8MQ, the system counter's clock frequency should be 8333333Hz. We use 25MHz OSC, so the freqency is 25/3. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tiberiu BreanaTiberiu Breana
77906fd1da1MLK-13855-3: perf: ddr-perf: Add counter overflow handling Added support for counter overflow interrupts. When the cycles counter overflows, update all local event data, then reset it and let it continue counting. Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com>
Tiberiu BreanaTiberiu Breana
7f3a24e2ecdMLK-13855-2: perf: ddr-perf: Always enable the cycles counter Always enable cycles counter 0, regardless if it is explicitly selected by the user or not. The cycles counter generates overflow interrupts that will be used to update other counters. Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com>
Tiberiu BreanaTiberiu Breana
fea5de6e459MLK-13855-1: perf: ddr-perf: Clean up driver - repurpose e2c_map array to a perf_event* array - add ddr_perf_event_enable function - tidy up indenting Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com>
Daniel BalutaDaniel Baluta
2b962044d1fMLK-14865: ARM: dts: imx6sx-sdb: Change audio PLL frequency for SSI Default frequency is 786432000 and we cannot derive an exact bitclk for 24 bits tests. This is similar with commit 9e3c04a3e9222a ("MLK-14781-2: ARM: dts: change audio pll frequency for ssi master mode"). Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Zhou Peng-B04994Zhou Peng-B04994
6efcb40e509MLK-15132-6 : Enable Hantro decoder on i.MX8MQ Enable vpu on imx8mq-evk dts file Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
Anson HuangAnson Huang
de2af1cc8d1MLK-15287 clk: imx: imx8mq: increase NOC clock speed NOC clock by default is running @400MHz, to achieve best DDR access performance, increase it to 800MHz. With CPU @1.2GHz, we can see stream copy performance increase 24% if NOC clock is increased from 400MHz to 800MHz. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Chenyan FengChenyan Feng
759f24e55a6MGS-3024 dts: update i.MX8MQ device config to enable GPU enable gpu device in imx8mq-evk board, increase GPU memory size from 32M to 128M, enable GPU flat mappping for full DDR range. add IMX8MQ_CLK_GPU_AHB_DIV into gpu clock list. Date: 26th June, 2017 Signed-of-by: Chenyan Feng <ella.feng@nxp.com>
Chenyan FengChenyan Feng
7ba6605565eMGS-3023 [#imx-623] add ahb clk operation for mscale gpu mscale gpu ahb clock has the different source from axi clock, need add the separate clock operation for gpu ahb in driver. Date: 24th June, 2017 Signed-off-by: Chenyan Feng <ella.feng@nxp.com>
Chenyan FengChenyan Feng
50fa4c329fdMGS-3021 [#imx-622] Disable gpu security feature for mscale GPU security feature is only for mscale, but driver is not ready, need disable this feature to avoid gpu kernel panic temporally, will drop this patch when gpu security driver is ready later. Date: 23th June, 2017 Signed-off-by: Chenyan Feng <ella.feng@nxp.com>
Anson HuangAnson Huang
94e81abcb19MLK-15285-2 soc: imx: add HAVE_IMX_SOC for soc driver soc driver is NOT only for i.MX8QM, add HAVE_IMX_SOC config to improve build dependency. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Anson HuangAnson Huang
a6148aad7e6MLK-15285-1 soc: imx: add i.MX8MQ soc id support Add i.MX8MQ SOC ID support, users can cat soc_id and revision via /sys/devices/soc0/: root@imx8mq:~# cat /sys/devices/soc0/soc_id i.MX8MQ root@imx8mq:~# cat /sys/devices/soc0/revision 1.0 Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Zhou Peng-B04994Zhou Peng-B04994
52f3947211eMLK-15132-5 : Enable Hantro decoder on i.MX8MQ Fix vpu decoder timeout issue: Enable clock before config VPUMIX registers Replace IMX8MQ_CLK_VPU_BUS_DIV with IMX8MQ_CLK_VPU_DEC_ROOT Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
Yong GanYong Gan
02704436d6bMGS-3025: ARM64: dts: freescale: imx8mq: enable viv drm Change CONFIG_DRM_VIVANTE to be "m". Date: Jun 26, 2017 Signed-off-by Meng Mingming <mingming.meng@nxp.com>
Leonard CrestezLeonard Crestez
9e7cb68a9b1MLK-15151: dma: imx-sdma: Fix keepings clks enabled on sdma_resume error This is obviously a bug but I don't know of a scenario where those errors might happen. Fixes: 7e84737c9c24 ("MLK-11385 dma: imx-sdma: enable clock before context restored") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Cristina CiocanCristina Ciocan
4a510a55f58MLK-15125: arm: dts: imx6sx: Fix duplicate name in lcdif lcdif2 node has a property called "display" and a subnode that is also called "display", leading to an OF duplicate warning at boot time. Fix this by changing the subnode's name to "display@1". Signed-off-by: Cristina Ciocan <cristina-mihaela.ciocan@nxp.com>
Fugang DuanFugang Duan
a7aa93ab873MLK-15148 ARM64: dts: freescale: imx8mq: add uart DMA chans and enable BT port Add uart DMA chans for imx8mq platform. Enable uart3 port for Bluetooth on evk board. Correct the earlycon name. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Fugang DuanFugang Duan
3524ae9f0fcMLK-15147 arm64: imx8mq: fix iomux header file uart pin issue imx8mq iomux header file uart part select_input config are wrong that cause most of uart pin not work. Add DCE and DTE string to distinguish the pin is for uart which function, and clear all select_input for output pin. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>