Commits
Anson Huang committed 840f955a156
MLK-15347 clk: imx: correct sccg and frac pll rate calculation error
- For SCCG SCCG_PLL2 type, its parent rate is with round-up,
using parent rate to calculate its rate will introduce
some error, like below sys1_pll2, its rate is actually 800M,
but we got 800000004:
sys1_pll1_ref_sel 1 1 25000000 0 0
sys1_pll1_ref_div 1 1 25000000 0 0
sys1_pll1 1 1 1600000000 0 0
sys1_pll1_out 1 1 1600000000 0 0
sys1_pll1_out_div 1 1 66666667 0 0
sys1_pll2 1 1 800000004 0 0
here we redo the calculation from top reference clk to
avoid the error, the result will be as below:
sys1_pll1_ref_sel 1 1 25000000 0 0
sys1_pll1_ref_div 1 1 25000000 0 0
sys1_pll1 1 1 1600000000 0 0
sys1_pll1_out 1 1 1600000000 0 0
sys1_pll1_out_div 1 1 66666667 0 0
sys1_pll2 1 1 800000000 0 0
- For FRAC PLL, the calculation formula is incorrect, the
divff should NOT add 1, fix it to get correct rate:
before fix:
arm_pll_ref_sel 1 1 25000000 0 0
arm_pll_ref_div 1 1 5000000 0 0
arm_pll 1 1 1200000001 0 0
after fix:
arm_pll_ref_sel 1 1 25000000 0 0
arm_pll_ref_div 1 1 5000000 0 0
arm_pll 1 1 1200000000 0 0
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>