MLK-15004: ASoC: fsl: Refactor DMA workaround
Commit 2f756e7aa8840 ("ASoC: fsl_esai: esai workaround for imx8qxp
Rev1") introduced a workaround for ESAI.
Because the same workaround needs to be done for SPDIF, we refactor
GPT handling in order to avoid code duplication.
Notice that we isolate code related to workaround into
fsl_dma_workaround so that only few lines of code from ESAI/SPDIF
are modified. Thus when the hardware issue will be fixed there will
be very little things to revert in...
MLK-15959: ASoc: fsl: fix hifi4 driver build warning
When building sound/soc/fsl/fsl_hifi4.c file, a warning
occurs:
warning: cast to pointer from integer of different
size [-Wint-to-pointer-cast]
(struct timestamp_info_t *)pext_msg->dtstamp;
By forced conversing int type to long type to fix this
issue.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
MLK-15955 gpu: imx: dpu: Sort dpu unit names in struct dpu_soc alphabetically
This patch sorts DPU unit names in structure dpu_soc alphabetically.
So, just code change only.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15951: ARM64: dts: fsl-imx8qxp: Fix SAI master clock assignment
The SAI driver maps the DTS master clock names to the registers settings
that select the audio Master Clock used for internally generated bit clock
when SAI operates in master mode.
The mapping is defined as follows:
mclk0 -> Bus Clock
mclk1 -> Master Clock (MCLK) 1
mclk2 -> Master Clock (MCLK) 2
mclk3 -> Master Clock (MCLK) 3
In iMX8QXP the SAIs are connected to MCLK 1 so we have to use it in DTS.
Signed-off-by: Mihai Se...
MLK-15953-04 ARM64: config: Enable i.mx8mq thermal driver support
Enable the thermal driver support in default config for i.MX8MQ
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15953-03 ARM64: dts: Add tmu thermal device node support for imx8mq
Add the tmu thermal zone device support on i.MX8MQ. At present, only
support one thermal zone, other two thermal zone support will be added
later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15953-02 driver: thermal: Add tmu thermal driver support for i.mx8mq
On i.MX8MQ, we use the same TMU as on QorIQ platform, so the TMU driver
for QorIQ platform can be resued on our i.MX8M platform.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15356-2:[i.MX8MQ/Hantro] Add support for android platform
Add compat ioctl for 32 bit application
This is re-commit: only reserve hantro driver change
remove mxc_ion change
Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
MLK-15325: pxp-v3: Modify pxp pitch parameter and csc
coefficient setting.
Because the caller of pxp-v3 does not set the stride parameter,
this will cause pitch parameter to be zero and pxp can't work.
Correct the csc1 coefficient when use pxp convert YUV to RGB format.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Revert "MLK-15356-2:[i.MX8MQ/Hantro] Add support for android platform"
This reverts commit b5d7e2af70d25568835a813a95032998194bc262 as it
breaks the build on imx6/7.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
MLK-15356-2:[i.MX8MQ/Hantro] Add support for android platform
Add compat ioctl for 32 bit application
Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
MLK-15932-8 drm/imx: dpu: kms: Add scalers support
This patch adds scalers support. According to the DPU spec, we only
support up-scaling for display controller.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15932-7 gpu: imx: dpu: common: Add scalers support in dpu plane group
This patch adds scalers support in dpu plane group. A module parameter,
i.e., display_plane_video_proc, is introduced to enable or disable video
processing capability of display plane, since some video processing units
are shared with capture controllers. By default, it is enabled.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15932-4 gpu: imx: dpu: fetchdecode: Add scaler support
The output of FetchDecode can be the input of HScaler and/or VScaler.
If both of the two scalers are wanted, the two scalers can be connected
with each other by themselves as an united scaler unit. This patch adds
basic scaling capability support for FetchDecode. Three helpers are
introduced - fetchdecode_get_vproc_mask() and fetchdecode_get_h/vscaler().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15932-3 gpu: imx: dpu: common: Add HScaler and VScaler support
This patch adds basic HScaler and VScaler support in the DPU core driver.
The two scaler units can be used in the display controller, blit engine
or capture controller. Currently, we only support the display controller.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15932-2 video: dpu: Remove the prefix 'lb_' for lb_pixengcfg_clken_t
There are several DPU units which have the same clock enable control bits
in their Dynamic registers, e.g., HScaler, VScaler, Rop, Fliter and Matrix,
etc. So, let's remove the prefix 'lb_' from the enumerator name of
lb_pixengcfg_clk_t so that it can be a little bit generic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15932-1 video: dpu: Add prefix 'LB_' to member names of enum lb_mode_t
The member name 'NEUTRAL' of enum lb_mode_t is a little bit too generic,
since others DPU units have neutral modes as well, e.g., HScaler, VScaler,
Rop, CLuT and Matrix, etc. So, let's add the prefix 'LB_' to member names
of enum lb_mode_t so that they can be specific to LayerBlends.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MA-9801 Add ION configure to DTS for 8qm&8qxp platform.
Enable ION function on 8qm&8qxp platform.
Change-Id: Ib217b57e4d0706143db34626ddfd1002a25ff2e9
Signed-off-by: ivan.liu <xiaowen.liu@nxp.com>
MLK-15938-3 arm64: dts: freescale: imx8mq: add pwm led support
i.MX8MQ EVK board has a PWM LED, add support for it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15938-2 arm64: defconfig: add imx pwm led support
Add CONFIG_LEDS_PWM and CONFIG_PWM_IMX support for
i.MX8MQ which has a PWM LED on EVK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15934-3: ASoc: fsl: add hifi4 firmware's status transfer support
1. add cases to receive error value from hifi4 firmware and
return this error to hifi4 driver's caller.
2. add cases to receive input over indicator variable from
hifi4 dirver's caller and pass this value to hifi4 firmware
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
MLK-15934-2: ASoc: fsl: different pointer length issue for hifi4
when transferring struct icm_open_resp_info_t type
between hifi4 framework and hifi4 driver, because this
struct has an element "*dtstamp" which is a pointer,
but for hifi4 firmware, this pointer occupies 4 bytes,
for hifi4 driver, this pointer occupies 8 bytes.
different pointer length will cause issue when reading
this structure's content in hifi4 driver.
By changing the pointer type to unsigned int type to
fix this issue.
...
MLK-15935-02 ARM64: configs: Enable trip point writable config for debug purpose
We may need to dynamically change the trip point temp for thermal driver validation,
so enable the trip point writable config in defconfig.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15935-01 ARM64: dts: update the critical trip point temp for 8qm/qxp
Update the default critical trip point temp to 127C to align with the
SCFW's panic alarm temp.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15940 video: fbdev: imx_northwest_dsi: refine the horizontal blanking periods.
The horizontal blanking periods should have bytes unit
instead of pixels.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-15335 clk: imx7d-ccm: Remove ARM_M0 clock
IMX7d does not contain an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
MLK-15927-2: ARM64: dts: iMX8QM and iMX8QXP use specific SAI compatibility string
For iMX8QM and iMX8QXP the SAI device driver must to add a constraint
on the period size because of EDMA requirements.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-15927-1: ASoC: fsl_sai: Fix noise when using EDMA
EDMA requires the period size to be multiple of maxburst. Otherwise the
remaining bytes are not transferred and thus noise is produced.
We can handle this issue by adding a constraint on
SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value.
This is based on a similar patch we have for ESAI:
commit bd3f3eb2a37c
("MLK-15109-2: ASoC: fsl_esai: add constrain_period_size")
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
...
MLK-15933 arm64: dts: freescale: imx8qm: update A72 cpu freq table
i.MX8QM SCFW fixes the HP PLL rate calculation, A72 cluster
CPU frequency has been changed from 1584MHz to 1596MHz,
change the CPU OPP table accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15925-3 drm/imx: dpu: kms: Avoid plane src hot migration between 2 disps
The DPU fetch units(backing DRM planes) are shared by two displays(a.k.a,
CRTCs). Since the shadow trigger/load mechanism of each display(CRTC)
is independent from each other, on-the-fly/hot migration of plane source
is likely to cause resouce conflict issue when the shadow registers are
loaded. This patch changes the way we assign fetch units for each DRM
planes so that we may avoid the migrations from happening....
MLK-15925-2 gpu: imx: dpu: fetchdecode: Add a helper to report if fd is enabled
This patch adds a helper so that users may know if the fetchdecode is enabled
or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15925-1 gpu: imx: dpu: fetchdecode: Add get/set display stream id support
This patch adds two helpers so that users may get or set the display
stream id of fetchdecode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15354 clk: imx: imx8mq: add video_pll2 clock
Add video_pll2 SSCG PLL clock in anamix which can
be used by HDMI and DCSS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-15748 drm/imx: dpu: plane: Correct the way we do framebuffer cropping
We should not use fetchdecode clip feature to do framebuffer cropping
since the hardware hehavior differs from what we expected.
According to the spec, it seems that the clip feature will keep the
source frame resolution and fill pixels in the clipped area. So, let's
take the usual way to do the cropping and just simply tweak the buffer
start address.
Reported-by: Jared Hu <jared.hu@nxp.com>
Tested-by: Jared Hu <jare...
MLK-15317-6: ARM64: dts: Add support for MQS in im8xp
We introduce a new dts for MQS which is supported by
imx8qxp with debug base board v2.
Connection in debug board is:
MQS_LEFT: SEAF_B_G39
MQS_RIGHT: SEAF_B_G38
This is similar with imx8qm. Note that these pins are shared with SPDIF.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-15317-3: ASoC: fsl_mqs: Add support for MQS dummy codec in imx8qxp
MQS on i.mx8 QXP uses the same register as i.mx8 QM
so we only need to add compatible string here.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-15317-2: ARM64: dts: Move AUD clocks under acm node
This mirrors change done for 8qm in commit c7c63a5d241b ("MLK-15340-4: ARM64: dts:
support SPDIF, MQS, SAI in imx8qm").
This needs to be moved out of esai node because esai node
might not be active all the time.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Mihai Serban <mihai.serban@nxp.com>
