Yocto Project Linux Firmware
  1. Yocto Project Linux Firmware

linux-wandboard

Public

Network

 
AuthorCommitMessageCommit Date
Fugang DuanFugang Duan
cd5a68f6b3bMLK-17133-03 tty: serial: lpuart: directly terminate rx dma chans in .shutdown() No need to wait dma_wait event, directly terminate rx dma chans in .shutdown() callback. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Fugang DuanFugang Duan
b3589c79d2cMLK-17133-02 tty: serial: lpuart: add runtime pm support Add runtime pm support to manage lpuart clock and its power domain to save power in system idle and system suspend stages. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Fugang DuanFugang Duan
ab861f7e05fMLK-17133-01 tty: serial: lpuart: only enable wakeup interrupt when wakeup enabled Current driver suppose system disable irq when wakeup is not enabled like below follow, so it always enable the wakeup interrupt in .suspend_noirq(). dpm_suspend_noirq() device_wakeup_arm_wake_irqs() if (device_may_wakeup(wirq->dev)) enable_irq_wake(wirq->irq); irq_set_irq_wake(irq, 1); suspend_device_irqs(); if (irqd_is_wakeup_set(&desc->irq_data)) __disable_irq(desc); device_suspend...
Dong AishengDong Aisheng
9e35d2aa946MLK-17124 imx8: pm-domains: fix clock rate may lost due to domain off during probe phase With current design, there may be a clock state issue lost due to driver probe fail and power domain go to OFF. Then the next driver probe using the same domain and clocks may fail because the kernel already caches the last clk settings, the next retry will return directly. As a result, driver may believe the the clk setting is passed but actually no in HW. So a state mismatach happenes between SW and HW...
Robby CaiRobby Cai
a978faa3c27MLK-17058 media: csi: fix spurious warning message When boot up with 4K HDMI display, and at same time do a capture with 720p (or above), meet following message. [ 241.572132] mx6s-csi 30a90000.csi1_bridge: 82300000 != 82300000 [ 241.604974] mx6s-csi 30a90000.csi1_bridge: 82700000 != 82700000 [ 241.638305] mx6s-csi 30a90000.csi1_bridge: 82b00000 != 82b00000 [ 241.704969] mx6s-csi 30a90000.csi1_bridge: 82300000 != 82300000 ... cast the type of unsigned long to unsigned int before compar...
Robby CaiRobby Cai
095553d487aMLK-17116-2 media: mipi_csi: Adjust hs_settle and send_level for low resolution Change the hs_settle and fifo_send_level setting for 640x480 and 720x480 input resolution. Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Sandor Yu <sandor.yu@nxp.com> (cherry picked from commit 3c081af366e250ff011319d80c5706ae7b8e38ca)
Robby CaiRobby Cai
6bb3da97657MLK-17116-1 media: camera: use simpler way for 20MHz mclk setting For ov5640, the simpler way is to make PLL1 same. Here's changing PRE_DIV0. "24MHz / 3" equals to "20MHz / 2.5", hereby the reg 3037[3:0] = 7. Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Sandor Yu <sandor.yu@nxp.com> (cherry picked from commit bf7d2bb06ca3bdf88a8aa86ac39b7d3f44134ea5)
Liu YingLiu Ying
9cebce41531MLK-15110-23 drm/imx: dpu: kms: Add prefetch support This patch adds prefetch support so that we may use prefetch engine where possible. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
2f85139a370MLK-15110-22 drm/imx: dpu: crtc: Evade the first dumb frame for DPR/PRG errata To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame which is generated by DPU. The way we achieve that is to bypass TCON(but set the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU display controller, and then enable the display controller, wait for the frame index starting to move and finally switch TCON to operation mode. Signed-off-by: Liu Ying <victor.liu@n...
Liu YingLiu Ying
5fc0f13a7fcMLK-15110-21 gpu: imx: dpu: framegen: Add timestamp support for frame index This patch adds framegen timestamp support for the frame index feature. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
a2a10097950MLK-15110-20 gpu: imx: dpu: fetcheco: Fixup stride when we use prefetch When we use prefetch, we use DPR and PRG to do frame input cropping. Thus, the stride of fetcheco is the stride of cropped frame, which means the value of the stride is cropped_width * bytes_per_pixel. Since the pixel format has to be NV12 or NV21 when we use prefetch, we assume the cropped_width stands for how many UV we have in bytes for one line, while bytes_per_pixel should be 8bits for every U or V component. Also...
Liu YingLiu Ying
372c36dd710MLK-15110-19 gpu: imx: dpu: fetchdecode: Fixup stride when we use prefetch When we use prefetch, we use DPR and PRG to do frame input cropping. Thus, the stride of fetchdecode is the stride of cropped frame, which means the value of the stride is cropped_width * bytes_per_pixel. Also, to address TKT339017, when we use prefetch engine for fetchdecode, we need to round the frame stride up to the fetchdecode burst size, i.e., burst length multiplies 8 bytes. According to TKT343664, the buffe...
Liu YingLiu Ying
54417817a0fMLK-15110-18 gpu: imx: dpu: fetcheco: Add helper fetcheco_set_burstlength() This patch adds helper fetcheco_set_burstlength() so that the burst length of fetcheco can be set to appropriate value. When we don't use prefetch engine, the burst length is set to the maximal value - 16. When we use prefetch engine, the burst length should make the buffer base address align to burst size but not greater than 16. This alignment operation can address the issue recorded by TKT343664. Signed-off-by:...
Liu YingLiu Ying
8dde832b6feMLK-15110-17 gpu: imx: dpu: fetchdecode: Add helper fetchdecode_set_burstlength() This patch adds helper fetchdecode_set_burstlength() so that the burst length of fetchdecode can be set to appropriate value. When we don't use prefetch engine, the burst length is set to the maximal value - 16. When we use prefetch engine, the burst length should make the buffer base address align to burst size but not greater than 16. This alignment operation can address the issue recorded by TKT343664. Si...
Liu YingLiu Ying
d5075c9f4d8MLK-15110-16 gpu: imx: dpu: fetcheco: Add helpers to set/get fetcheco off pin This patch adds some helpers to set/get fetcheco off pin. We need to pin fetcheco off when the primary plane is disabled and the relevant fetcheco is feed by prefetch engine. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
38bbb3717aaMLK-15110-15 gpu: imx: dpu: fetchdecode: Add DPR support This patch adds DPR support for fetchdecode in the DPU base driver. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
840daf1ef72MLK-15110-14 arm64: dts: fsl-imx8qxp-mek: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
506b5b70629MLK-15110-13 arm64: dts: fsl-imx8qxp-lpddr4-arm2: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
4562ec7b2dcMLK-15110-12 arm64: dtsi: fsl-imx8qxp: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
28829fbec1dMLK-15110-11 arm64: dtsi: fsl-imx8qxp: Add DPR0/1 irq resources for DPU The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU. This patch adds the DPR0/1's irq resources for DPU. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
d0763c72d86MLK-15110-10 clk: imx: clk-imx8qxp: Add IMX8QXP_DC0_DPR1_APB/B_CLK support This patch adds IMX8QXP_DC0_DPR1_APB_CLK and IMX8QXP_DC0_DPR1_B_CLK clocks support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
3b462d2de25MLK-15110-9 arm64: dts: fsl-imx8qm-mek: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
6b244f212a1MLK-15110-8 arm64: dts: fsl-imx8qm-lpddr4-arm2: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
920a58a5e42MLK-15110-7 arm64: dtsi: fsl-imx8qm: Add DPR and PRG support This patch adds DPR and PRG support. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
fc0d009f692MLK-15110-6 arm64: dtsi: fsl-imx8qm: Add DPR0/1/2/3 irq resources for DPU0/1 The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU. This patch adds the DPR0/1/2/3's irq resources for DPU0/1. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
751ddf9af7bMLK-15110-5 gpu: imx: dpu: Name inner DPU interrupts explicitly We will support DPR interrupts via DPU core driver. In order to distinguish bewteen the inner DPU interrupts and the DPR interrupts, let's rename some software stuffs which are related to DPU interrupts so that they may show they are DPU inner explicitly. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
d9682ba853dMLK-15110-4 gpu: imx: dpu: Select IMX8_PRG and IMX8_DPRC in Kconfig Since we needs to use PRG and DPR in DPU base driver, let's select the two drivers when we enable DPU. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
a0a3a82f90eMLK-15110-3 gpu: imx: Add i.MX8 DPR(Display Prefetch Resolve) support The Display Prefetch Resolve(DPR) is a processor of fetching display data before the display pipeline which needs data to drive pixels in the active display region. The data is transformed, or resolved from a variety of tiled buffer formats into linear format. The DPR transaction sequences are issued with a high level of DRAM efficiency. This patch adds the base driver support for i.MX8qm/qxp DPR. Signed-off-by: Liu Yi...
Liu YingLiu Ying
b282aee0753MLK-15110-2 gpu: imx: Add i.MX8 PRG(Prefetch Resolve Gasket) support The Pretch Resolve Gasket(PRG) is a digital core function as a gasket interface between RTRAM controller and DPU. The main function of PRG is to convert the AXI interface to RTRAM interface and remapping the ARADDR to a RTRAM address. This patch adds the base driver support for i.MX8qm/qxp PRG. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
1fe6f5197cbMLK-15110-1 drm/fourcc: Add Amphion tiled layout format modifier Amphion VPU has a tiled layout using 8x128 pixel vertical strips, where each strip contains 1x16 groups of 8x8 pixels in a row-major layout. Signed-off-by: Song Bing <bing.song@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Sandor YuSandor Yu
b91edd51b2aMLK-17126-6: arm64 dts: Add hdmi dts for imx8qm mek Add fsl-imx8qm-mek-hdmi.dts for imx8qm mek board. BuildInfo: - SCFW e0362348, IMX-MKIMAGE 9841373a, ATF e173337 - U-Boot 2017.03-imx_v2017.03+g3535868 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Sandor YuSandor Yu
fde91126f66MLK-17126-5: arm64 dts: Move hdmi compatible srting Move imx8qm hdmi/dp compatible srting from soc specific dts to board specific dts. BuildInfo: - SCFW e0362348, IMX-MKIMAGE 9841373a, ATF e173337 - U-Boot 2017.03-imx_v2017.03+g3535868 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Sandor YuSandor Yu
6f622035fedMLK-17126-4: hdp: Fix V/Hsync polarity issue Remove v/hsync polarity adjust function. Add pixel link mux configuration function for imx8qm. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Sandor YuSandor Yu
58702e616caMLK-17126-3: hdmi api: Fix h/v sync polarity issue Fix H/V Sync polarity issue. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Sandor YuSandor Yu
70aa7cd6446MLK-17126-2: hdp: Support imx8qm HDMI function Add phy reset before hdmi/dp phy init. Reparent hdmi pixel clock to av_pll. Combine DP and HDMI ipg clock function. Add DP and HDMI pixel clock set rate function. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Sandor YuSandor Yu
5a5ca78ef2eMLK-17126-1: hdp api: workaround for imx8qm HDMI DDC R/W issue HDMI DDC R/W function is not supported by imx8qm HDMI FW. Skip the function for imx8qm before the issue is fixed in FW. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Peter ChenPeter Chen
56ecab740e9MLK-16976-6 ARM64: dts: fsl-imx8qxp: let USB have wakeup capability Let PM code know USB has wake system up capability. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Peter ChenPeter Chen
19bd13fa279MLK-16976-5 ARM64: dts: fsl-imx8qxp-mek: add 12V source capability for Type-C The MEK hardware design supports 12V power source, update src-pdos for it. And It doesn't support power sink, so remove additional sink PDOS setting. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Peter ChenPeter Chen
2354479289cMLK-16976-4 usb: cdns3: add power management support This patch set adds both runtime and system-level pm support. For runtime-pm: both host and device wakeup events are supported. For system-pm: only host wakeup events are supported, device wakeup events are from other peripherals, and will support later. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Peter ChenPeter Chen
efe0607fafcMLK-16976-3 ARM64: dts: fsl-imx8qm-mek: add USB support - USB2 Dual-role support, and below rework is needed: Remove R295, R296, R122, and install R116, R117, R127 - USB3 Dual-role support BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Peter ChenPeter Chen
ca4eb844cf0MLK-16976-2 ARM64: dts: fsl-imx8qm: let USB have wakeup capability Let PM code know USB has wake system up capability. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Peter ChenPeter Chen
8d69e469e68MLK-16976-1 ARM64: dts: fsl-imx8: add OTG register regions for Cadence USB3 Add OTG register regions for Cadence USB3. BuildInfo: - SCFW 245582b, IMX-MKIMAGE 0ad6069a, ATF 6bd98a3 - U-Boot 2017.03-imx_v2017.03+gfa65b0a Acked-by: Jun Li <jun.li@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com>
Viorel SumanViorel Suman
3218e35fb89MLK-17089-8: ASoC: fsl_amix: support suspend & resume for imx8 Base on latest power management design in MLK-17074, every driver need to enter runtime suspend state in suspend, so the driver should call the pm_runtime_force_suspend in suspend. With this implementation the suspend function almost same as runtime suspend function. so remove the suspend function, just use pm_runtime_force_suspend instead. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu...
Robert ChirasRobert Chiras
0c2643a00b9MLK-17117: arm64: dts: fsl-imx8mq-evk: Add support for dual-display Add a DTS file which will have both the lcdif and dcss nodes enabled and configured. The DCSS will work with HDMI output, while the eLCDIF will work with ADV7535 DSI-HDMI converter. Also, remove lcdif-rm67191.dts from Makefile, since lcdif is limited to 720p. This combination is no longer working, until we have the timings for 720p for the MIPI panel. Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Robert ChirasRobert Chiras
a672d8e5eeeMLK-17090: drm/mxsfb: Update mxsfb with additional pixel formats Since version 4 of eLCDIF, there are some registers that can do transformations on the input data, like re-arranging the pixel components. By doing that, we can support more pixel formats. This patch adds support for X/ABGR and RGBX/A. Although, the local alpha is not supported by eLCDIF, the alpha pixel formats were added to the supported pixel formats but it will be ignored. This was necessary since there are systems (like An...
Yuchou GanYuchou Gan
c45a0b0e205MGS-3495 [#imx-701] gpu failed to power off when nothing to be update Merge fix patch from VSI. Tested on wayland,the power could be cut off in a few seconds, if ctrl + c to terminate a running program making gpu idle Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@nxp.com> Reviewed-by: Yuchou Gan <yuchou.gan@nxp.com> Reviewed-by: Xianzhong <xianzhong.li@nxp.com>
Li JunLi Jun
11fa381b145MLK-17110 usb: dwc3: use system_freezable_wq for role change work To avoid deadlock after system resume if the role changes notification is sent while system resume, we need to drain the work handling until thawed. Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
Badhri Jagan SridharanBadhri Jagan Sridharan
610aba6ffacstaging: typec: tcpm: Do not send PING msgs in TCPM PING messages are used to monitor the connect/disconnect. However, when PD is carried over CC, so this is not required. Also, the spec does not clearly say if PD is possible when Type-c is connected to Type-A/B. So, removing sending PING messages altogether. Signed-off-by: Badhri Jagan Sridharan <Badhri@google.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked...
Liu YingLiu Ying
6650de955e9MLK-17112 gpu: imx: dpu: Ensure the dpu core is late suspended & early resumed The dpu core driver needs to do some cleanup work for the upper layer drivers, so it should be late suspended and early resumed. This patch ensures this by changing driver PM hook definitions to use SET_LATE_SYSTEM_SLEEP_PM_OPS instead of SET_SYSTEM_SLEEP_PM_OPS. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bai PingBai Ping
56893d54a6dMLK-17104 drivers: clk: imx: change the VPU related clock flags of imx8mq When the system reaches the passive critical trip point, VPU device cooling need to change the clock rate on the fly. So change the VPU related clocks flags to make sure the clock rate can be changed successfully. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>