linux-wandboard

MLK-17124 imx8: pm-domains: fix clock rate may lost due to domain off during probe phase

With current design, there may be a clock state issue lost due to driver
probe fail and power domain go to OFF. Then the next driver probe using the
same domain and clocks may fail because the kernel already caches the last clk
settings, the next retry will return directly. As a result, driver may believe
the the clk setting is passed but actually no in HW. So a state mismatach
happenes between SW and HW.

This is actually a nature limitation with current design as there's no state
alignment mechanism between clk SW status and HW status. Power Domain and CLK
subsystem are two separate subsystems in current kernel design, re-architecure
the kernel power domain and clk probably is the best way to handle this issue.

However, this patch implements a quick workaround to trap the possible state
lost case and give the driver one more chance to re-set the clk when power
domain is enabled. This can tempororily fix this issue although may be not
be so good from architecture point of view.

One note is that as a parent clk rate restore will cause the clk recalc
to all possible child clks which may result in child clk previous state lost
due to power domain lost before,  we have to first walk through all child clks
to retrieve the state via clk_hw_get_rate which bypassed the clk recalc,
then we can restore them one by one.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>