MLK-17128-1 dt-bindings: typec: add max_snk_mw property
Add max_snk_mw property for power sink to know the max power.
Because the max mw may be smaller than the max ma multiplied by
max mv:
max-mw <= max-mv*max-ma
After the power sink decides the PDO from source, it needs
to check the power to see if the provided power of this PDO
can match its requirement, which needs consider max_snk_mw to
know the max current it can have based on selected voltage.
Acked-by: Peter Chen <peter.chen...
MLK-17203 usb: host: xhci-plat: fix high bus freq release mismatch
If the xhci platform device is already suspended, we can't
release high bus freq again, fix the high bus count mismatch.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
MLK-17204 drm/imx: dpu: Add suspend/resume support for dpu-blit
Add suspend/resume support for dpu bliteng device.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
MLK-14897-3: clk: imx7d: Do not set rate for enet-axi in the ccm driver
Do not set rate for enet-axi in the ccm driver.
The device-tree set-rate attribute should be used instead.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
MLK-14897-2: clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRC
Cherry picked from upstream commit 1fd92dbaabe3 ("clk: imx7d: do not set
the parent of IMX7D_ENET_AXI_ROOT_SRC")
Booting the kernel on a imx7s-warp leads to several warnings like these:
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330
[ 0.000000] releasing a pinned lock
[ 0.000000] -----------...
MLK-14897-1: clk: imx7d: do not set parent of ethernet ref clocks
This is a rebase ot upstream commit:
'commit 5e33ebff7edd ("clk: imx7d: do not set parent of ethernet
time/ref clocks")':
"clk: imx7d: do not set parent of ethernet time/ref clocks
All device trees currently in mainline specify the time clock parent
using the assigned-clocks/assigned-clock-parents method, there is no
need to statically assign the parent in the core clock driver.
Also all current boards pr...
MLK-14897-0: imx7d: dts: Add enet_axi and enet_phy clock parents and rates
Add clock parents and rates for enet_axi and enet_phy in dts via
the asigned-parents and assigned-rates attributes.
These were previously set in the ccm driver via set_parent/set_rate
calls but that has been removed in upstream linux.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
MLK-17190 driver: soc: Fix audio bus mode clock rate on imx8mq
If the system is currently in low bus mode, if the audio device
request the audio bus mode, the NOC, AHB and AXI bus clock rate
will be set wrongly, then bus will run at very low frequency, then
lead to audio playback underrun.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Anson Huang <anson.huang@nxp.com>
MLK-17188-2 ARM64: dts: imx8qxp: assign usdhc clock parent
Assign i.MX8QXP uSDHC clocks parent to from PLL1.
This is a workaround for i.MX8QXP usdhc, PLL0 of CONN SS is not
stable sometimes, root cause is still under investigation in
design team. Now change to source from PLL1. Due to PLL1 is
1000MHz, so EMMC HS400ES mode can only work at 166MHz, compare
to the former 198MHz, the performance has small drop, read
performance drop about 10%, write performance drop about 6%.
SD do not has this...
MLK-17158-3 arm64: dts: imx8mq: Add a RAWNAND dedicated DTS for ARM2
Add fsl-imx8mq-ddr4-arm2-gpmi-nand.dts which enables the RAWNAND on
i.MX8MQ DDR4 ARM2 board.
Signed-off-by: Ye Li <ye.li@nxp.com>
MLK-17158-2 arm64: dts: imx8mq: Add gpmi and apbh-dma nodes
Add gpmi and apbh-dma nodes to i.MX8MQ DTSi. Both are used by RAWNAND driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
MLK-17158-1 drivers: clk: imx: Add RAWNAND root clock
i.MX8MQ CCGR has a clock enable signal for RAWNAND. Add this RAWNAND root
clock to clock tree.
Signed-off-by: Ye Li <ye.li@nxp.com>
MLK-17136 ath10k: clear fetch board fail log
Below fail log is caused by firmware version issue.
"ath10k_pci 0000:01:00.0: failed to fetch board data"
To clear the log, ath10k_dbg is used to replace ath10k_err.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-17152: ASoC: fsl_hifi: support suspend and resume
For hifi need to enter runtime suspend state in suspend,
then the power of HIFI can be down. In this case content
in internal RAM will be lost, and need to be recovered
in resume.
Move the loading firmware to runtime resume function, and
define ICM_SUSPEND and ICM_RESUME command, with ICM_SUSPEND
the hifi framework will store the data in RAM and with
ICM_RESUME the hifi framework will restore the data to RAM.
Signed-off-by: Shengjiu Wan...
MLK-16715-10 ARM64: dts: fsl-imx8qxp: change properties for USB2
The changes include: compatible, performance tuning parameters,
and delete the property which is dedicated to imx7d.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-9 ARM64: dts: fsl-imx8qm-lpddr4-arm2-hsic: add HSIC board dts
Some special for HSIC usages:
- It needs imx8 debug board to test HSIC function.
- The USBOTG1 needs to be active when HSIC is in use.
BuildInfo:
- SCFW e0362348, IMX-MKIMAGE 9841373a, ATF e173337
- U-Boot 2017.03-imx_v2017.03+g3535868
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-8 ARM64: dts: fsl-imx8qm: add USB HSIC support
Add USB HSIC controller support.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-7 usb: chipidea: imx: add "ci-disable-lpm" quirk
Some chipidea hardware needs to disable low power mode for controller
due to IC issue or hardware issue, add one quirk for it.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-6 usb: chipidea: imx: add HSIC support for controllers from imx7d
From imx7d, there is a dedicate non-core register region for
each controller, and HSIC configurations are almost at non-core
register, this commit adds HSIC support for controllers from imx7d,
and the non-core confugrations are different with imx6's.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-5 usb: chipidea: imx: using phy_mode to judge HSIC controller
HSIC controller must use HSIC phy mode, it is more suitable way
to judge HSIC controller.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-4 usb: chipidea: imx: add imx8qm compatible
It is suitable for imx8qm and imx8qxp currently
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-3 ARM64: dts: fsl-imx8qm: change USB2 controller properties
The imx8qm's non-core register controller is more like imx7ulp than
imx7d, since imx7d uses Samsung PHY, but imx7ulp and imx8qm use
freescale PHY, so imx8qm uses the same compatible for imx7ulp.
But imx8qm and imx7ulp's platform are so many differences, so the
compatible for driver are different.
Besides, we add performance tuning parameters and delete properties which
is dedicated for imx7d.
Acked-by: Jun Li <jun.li@nx...
MLK-16715-2 binding-doc: usb: ci-hdrc-usb2: add imx7ulp and imx8qm compatible
Add imx7ulp and imx8qm compatible.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16715-1 usb: chipidea: imx: replace &pdev->dev with local variable
There are tens of &pdev->dev, replace them with a local
variable
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-17149-2: arm64: dts: fsl-imx8mq.dtsi: Remove dummy clocks from lcdif
Apparently, the CLK_DUMMY implementation is not so reliable, since this
can occur when doing a clk_disable_unprepare on a CLK_DUMMY clock:
[ 51.197744] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W
4.9.51-03878-g6c48bec #415
[ 51.206354] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 51.211405] Call trace:
[ 51.213868] [<ffff0000080884c8>] dump_backtrace+0x0/0x1a0
[ 51.219273] [<ffff00000808867c>] show_stack...
MLK-17149-1: drm/mxsfb: Fix pipe enable
During enable function, the mxsfb driver is trying to associate with a
connector, when a drm_bridge is used. When accessing the connectors
list, mode_config->mutex might be locked, generating the below WARN.
Since we are not changing the mode_config, we can access the
connector_list directly.
[ 16.876991] [<ffff0000086289d4>] mxsfb_pipe_enable+0xec/0xf8
[ 16.882650] [<ffff0000085e4de0>] drm_simple_kms_crtc_enable+0x20/0x30
[ 16.889090] [<ffff000...
MLK-17111-2: crypto: caam: Enable caam job ring 2 for i.MX8 mScale
As required by Test/Validation Team the third job ring is enabled
here. This was not possible before modifying JR Master ID in ATF.
ATF (arm-trusted-firmware) should be updated before using this JR.
Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
MLK-17111-1: crypto: caam: Fix RNG instantiation retry
Seen on i.MX8MQ EVK board revision B0 that the RNG instantiation
fail with default entropy delay. Retry process is fixed here to
be able to instantiate RNG successfully.
Reviewed-by: Silvano Di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
MLK-17144 driver: soc: use mutex for power domain of imx8mq
In current gpc-psci.c file, the irqchip driver and gpc power
domain driver use the same spinlock to prevent concurrent
access to the GPC module. But actually, the irq and power domain
are two seperated function and controlled by different registers.
when using the same spinlock for these two funcition, in some corner
case the system will be deadlock if the spinlock is already acquired
by the power domain, but the power domain on/of...
MGS-2914 [#imx-587] [8QM/qxp] Disable depth compression only for 8QM
Disable the depth compression on device tree for 8qm/8qxp/mscale
when the ddr4 is enabled.
Date: Dec 11, 2017
Signed-off-by Yuchou Gan yuchou.gan@nxp.com
MLK-17147 arm64: dts: imx8mq: Add DDR3l and DDR4 ARM2 boards support
Add two DTS files for supporting DDR3l and DDR4 ARM2 boards. Basic
nodes like UART, SD/eMMC, i2c, Ethernet are added.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
MLK-17142 arm64: dts: 8qxp: introduce dom0 dts
Introudce dom0 dts.
disable rtc, we do not have sip handler in xen, also need to modify the
driver to use hvc call.
remove gpu ss reg property to avoid overriding dom0 mapping.
Modify lpuart0 interrupt-parent to use gic, because xen could only
handle gic.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
MLK-16549-2: ISI: fix suspend/resume error issue
Because ISI runtime suspend has disable clock before system
suspend. If driver does not know that and disable clock again
in system suspend callback. It will lead to isi clk count mis-
match.
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
MLK-16549-1: mipi_csi: fix camera sensor i2c R/W issue
Because there is a level shifter between mipi csi controller
and max9286 camera sensor bridge. We need configure RESET_B
and ENABLE pins as GPIO, otherwise the bridge will not work
normally.
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
MLK-17121: mtd: fsl-flexspi: re-init the flexspi after suspend/resume
re-init the flexspi controller after suspend/resume.
runtime resume will re-init the controller, Once the it was initialized
and need to be re-init(determined by read specific register bit).
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-17138: arm64: dts: sl-imx8qm.dtsi: Quad display support for 8QM
Add DTS files fo quad display on 8QM boards. Currently, there is only
one file for this: fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, which is
the combination for 2 LVDS + 2 MIPI-HDMI on LPDDR4 board.
This patch adds the other possible use-cases:
- 2 LVDS + 2 MIPI-Panel on LPDDR4
- 2 LVDS + 2 MIPI-HDMI on MEK
- 2 LVDS + 2 MIPI-Panel on MEK
Also:
- fix the fsl-imx8qm-lpddr4-arm2-it6263-adv7535.dts, since it
contained the old m...
MLK-17137-2: drm/bridge: Fix bridge_detach for nwl-dsi
When the bridge is detached from it's parent, we also need to unregister
the dsi_host. Also, in enable, check if we have a panel or a bridge
connected, otherwise enable is not needed.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17137-1: drm/imx: Fix unbind for nwl_dsi-imx
In unbind function, first we need to detach the bridge, then do the
encoder cleanup, so that the bridge will do a proper detach.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17047-2: drm/imx: Fix suspend/resume for nwl_dsi-imx
This patch addresses two issues:
1. Always request/release bus_freq, not just on suspend/resume routines
2. Check if the driver is running when doing a suspend, so that we won't
enable it by mistake on resume.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17047-1: drm/mxsfb: Fix suspend/resume
MXSFB should always request bus_freq when enabled and release bus_freq
when disabled. Also, when suspend/resume occurs, check if the driver is
running, so what we won't enable it by mistake in resume.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17115: drm/mxsfb: Add support for vblank
Currently, the vblank support is not correctly implemented in MXSFB_DRM
driver. Thix patch addresses this issue, so that vblank will be
supported by MXSFB_DRM driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17805: drm: imx: dcss: fix resume without HDMI cable
When no HDMI cable is in, the device is runtime suspended. Hence,
there's nothing to resume in this case.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17140-2: drm: imx: dcss: Change CTXLD trigger values
After activating the PM QoS, the old triggers didn't work anymore. Also,
this will remove a hardcoded value that might not work for all
resolutions.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MMFMWK-7806: drm: imx: dcss: check up/down scale ratios
When scaling up/down, DCSS has limits that cannot be exceeded. This
patch adds checks before the plane is updated and rejects those planes
that exceed the up/down scale limits.
Currently, the limit is 3:1 for downscaling and 1:3 for upscaling for
both video and graphics channels.
When support for WR_SCL/RD_SRC will be added, these limits will increase
to the following values:
* video: 7:1 downscale, 1:7 upscale
* graphics: 5:1 downs...
