Commits
Anson Huang committed 6ccf38c0745
MLK-17188-2 ARM64: dts: imx8qxp: assign usdhc clock parent Assign i.MX8QXP uSDHC clocks parent to from PLL1. This is a workaround for i.MX8QXP usdhc, PLL0 of CONN SS is not stable sometimes, root cause is still under investigation in design team. Now change to source from PLL1. Due to PLL1 is 1000MHz, so EMMC HS400ES mode can only work at 166MHz, compare to the former 198MHz, the performance has small drop, read performance drop about 10%, write performance drop about 6%. SD do not has this side effect. When PLL0 unstable issue is fixed, will change back to use PLL0. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Tested-by: Haibo Chen <haibo.chen@nxp.com>