MLK-15140-5: ARM64: dts: enable wm8524 and sai2
enable wm8524 and sai2
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15140-4: clk: clk-imx8mq: Add audio ipg clock
add audio ipg clock, sai ipg clock and correct some wrong
place in clock tree.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15140-3: ASoC: codecs: add wm8524 codec driver
Add wm8524 driver, there is no i2c interface for it.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15140-2: ASoC: fsl: add machine driver for wm8524
This a simple machine driver for wm8524.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15140-1: ASoC: fsl_sai: support latest sai module
The version of sai is upgrate in imx8mq, which add two register
in beginning, there is VERID and PARAM. the driver need to be
update
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15137-02 driver: clk: Remove new_div_ack check in frac pll
If the frac pll is powrer down or hold in reset, new_div_ack
will not be assert. Waiting for ack will failed.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15028: ASoC: codecs: wm8960: Remove bitclk relax condition
Using a higher bitclk then expected doesn't always work.
Here is an example:
aplay -Dhw:0,0 -d 5 -r 48000 -f S24_LE -c 2 audio48k24b2c.wav
In this case, the required bitclk is 48000 * 24 * 2 = 2304000
but the closest bitclk that can be derived is 3072000.
Now, for format S24_LE, SAI will use slot_width = 24, but since
the clock is faster than expected, it will start to send bytes
from the next channel so the sound will be corr...
MLK-15135-5 ARM64: configs: defconfig: enable imx-sdma driver on i.mx8
enable sdma driver on i.mx8 defconfig.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
MLK-15135-1: dma: imx-sdma: fix build warning on aarch64
fix below build warning with aarch64:
drivers/dma/imx-sdma.c: In function ‘sdma_prep_dma_cyclic’:
drivers/dma/imx-sdma.c:1727:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 5 has type ‘size_t’ [-Wformat=]
dev_dbg(sdma->dev, "entry %d: count: %d dma: %pad %s%s\n",
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
MLK-15133-02 driver: clk: Skip enable non-critical clks on imx8mq
Only enable the system critical clks by default, other clks only
need to be enabled when it is used by the driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15133-01 driver: clk: Enhance the frac&sccg pll code on i.mx8mq
1. Fix coding typo.
2. Add PLL lock check and fix the reload of divfi and divff for frac pll.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
MLK-15067: ASoC: fsl: imx-wm8958: Refactor GPR parsing
This is similar with commit c79a82aec8ccf ("ASoC: fsl: imx-wm8960: Refactor
GPR parsing") and it is needed for easier adding support for non-gpr boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-15131-1 defconfig: enable SNVS RTC
Enable SNVS RTC for i.MX8MQ by default.
The change of CONFIG_I2C_MUX is introduced by
running savedefconfig.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-15128-3 pinctrl: freescale: support scu and memmap pinctrl together
As i.MX8MQ is a ARM64 SoC but it does NOT use SCU pinctrl, so
need to support both SCU and MEMMAP pinctrl together for ARM64
build.
use IMX8_USE_SCU flag to distinguish SCU and MEMMAP pinctrl
type.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
MLK-14765: Fix DCP Aes timeout issues when used with CTS
The DCP driver does not obey cryptlen, when doing CTS this results in
passing to hardware input stream lengths which are not multiple of
block size. This causes the hw to misbehave. Also not honoring
cryptlen makes CTS fail. A check was introduced to prevent future
erroneous stream lengths from reaching the hardware. Code which is
splitting the input stream in internal DCP pages was changed to obey
cryptlen.
Signed-off-by: Radu Solea ...
MLK-14765: Fix DCP SHA null hashes and output length
On imx6sl and imx6ull DCP writes at least 32 bytes in the output
buffer instead of hash length as documented. Add intermediate buffer
to prevent write out of bounds.
When requested to produce null hashes DCP fails to produce valid
output. Add software workaround to bypass hardware and return valid output.
Signed-off-by: Radu Solea <radu.solea@nxp.com>
MGS-2949 [#ccc] revert power management workaround for imx8
SCFW crash is fixed, need drop the temporal workaround.
Date: Jun 07, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
MGS-2970-2 [#imx-603] fix dual gpu hang with power management
gpu1 hang is reproducible when run es32 cts with power mangement.
there is the gpu1 power-off/up when commit gpu0 and gpu1 early or late,
then gpu0 will break the inter-semaphore & stall from gpu1, and end up,
when gpu1 execute its command, will stuck to wait for gpu0 infinitely.
prevent the unexpected power-off bofore command commit on dual cores.
Date: Jun 18, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
MGS-2970-1 [#imx-603] fix dual gpu hang with power management
gpu mode is lost after power-off, hence gpu hang in dual mode,
this patch can configure gpu mode for each power-up properly.
Date: Jun 09, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
MGS-2857-2 [#imx-530] cleanup spinlock debug code from gpu kernel
not make sense to use the different codes for spinlock debug
Date: Jun 07, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
MLK-14663-2: ASoC: fsl: imx-wm8960: Kill warning for non-gpr boards
A side effect of commit 5555277e693a7 ("MLK-13574-1: ASoC: imx-wm8960:
remove the gpr dependency") is that a warning was printed for boards
without gpr. This can be confusing.
imx7d boards do not have a gpr setting, so use imx7d-evk-wm8960
compatible string to avoid printing the warning.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-14663-1: ASoC: fsl: imx-wm8960: Refactor GPR parsing
Refactor GPR handling into a function for easier adding support
for non-gpr boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
