MLK-16015-4 gpu: imx: dpu: framegen: Add pixel link enable/disable logics
To enable or disable a display safely, we need to enable pixel link
after framegen is enabled and disable pixel link before framegen is
disabled. These operations are recommended by the design team.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-3 arm64: fsl-imx8qm.dtsi: Add ldb aliases
This patch adds ldb aliases so that the relevant driver is
able to distinguish between the two LDB instances.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-2 phy: mixel-lvds-combo: Add delay to wait PHY to be locked
It seems that we haven't got SCU ISO bit available to check if PHY is
locked or not after enable, so let's simply delay for a while as a
temporary solution.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-1 phy: mixel-lvds: Add delay to wait PHY to be locked
It seems that we haven't got SCU ISO bit available to check if PHY is
locked or not after enable, so let's simply delay for a while as a
temporary solution.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15973 ARM: dts: imx6sx-sabreauto: correct CD pin.
Correct the CD pin for baseboard SD slot, otherwise
the card detection can't work.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
usb: host: xhci-ring: don't need to clear interrupt pending for MSI enabled hcd
According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram
If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled,
then the assertion of the Interrupt Pending (IP) flag in Figure 30
generates a PCI Dword write. The IP flag is automatically cleared
by the completion of the PCI write.
the MSI enabled HCs don't need to clear interrupt pending bit, but
hcd->irq = 0 doesn't equ...
usb: host: xhci: delete sp_dma_buffers for scratchpad
We already have sp_array to store each scratch buffer address for xHC,
it doesn't need another sp_dma_buffers array to store it.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
MA-9931 [#imx-667] use kzalloc instead of kmalloc during fence_init.
Fix cts android.app.uiautomation.cts.UiAutomationTest#testWindowContentFrameStats fail.
This case check fence getSignalTime, which is get from fence->timestamp.
If use kmalloc, timestamp value is not guaranteed and can't be updated during fence_signal.
Date: Jul 17, 2017
Signed-off-by: juan.hao <juan.hao@nxp.com>
MGS-2966 [#imx-651] fix GPU hang with power management off
iMX8QXP SCFW has the strict requirement on GPU power-up/down flow,
when GPU power management is disabled, there is no power-down,
then GPU hang with the second power-up when insmod galcore.
this fix will enable power-down when unload galcore module.
Date: Jul 07, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
MLK-15995 imx: mlb: only use irq_ahb1 for imx6
Due to IP integration difference, there are 2 ahb irqs
for imx6 and only 1 ahb irq for imx8. This patch makes
mlb driver compatible with irq difference.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-15992 imx: mlb: add ipg & hclk clocks for imx8 mlb
Add ipg & hclk clock for imx8 mlb due to IP integration difference.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-15988 imx: mlb: remove clk for mlb 6 pin mode
mlb 6 pin mode is not supported in current release,
so remove clk for mlb 6 pin mode.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-15987 imx: mlb: use dma pool when iram doesn't exist
alloc mlb data buffer from dma pool when iram doesn't exist
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-13975: ASoC: fsl_sai: Refine master flag handling
The patch introduces the master flag handling
as function of direction and the option to provide
the flag value from DTS.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
MLK-16005-2 arm64: tlb: add the SW workaround for i.MX8QM TKT340553
on i.MX8QM TO1.0, there is an issue: the bus width between A53-CCI-A72
is limited to 36bits.TLB maintenance through DVM messages over AR channel,
some bits will be forced(truncated) to zero as the followings:
ASID[15:12] is forced to 0
VA[48:45] is forced to 0
VA[44:41] is forced to 0
VA[39:36] is forced to 0
This issue will result in the TLB aintenance across the clusters not working
as expected due to some VA and ASID bi...
MLK-16005-1 drivers: soc: refine the imx8 soc revision support
This patch is to refine the imx8 soc revision support. The imx8qm and
imx8qxp will go through the SCU API to get the silicon ID and REVISION.
imx8mq will go through the anatop interface to get the ID/REV.
Since the silicon ID/REV need be set as early as possible, thus refine it
by using the early_initcall for the early initialization. For the SCU API
interface, this need be called after the MU interface initialized.
Signed-off-...
MLK-15980: Revert "ASoC: imx-wm8962: Use a lower FLL output rate for S20_3LE and S24_LE formats"
This reverts commit be13ac391d27c925 ("MLK-15101: ASoC: imx-wm8962: Use a lower
FLL output rate for S20_3LE and S24_LE formats").
This breaks recording. We'll have to find a better fix for MLK-15101.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-16001 drm/imx: dpu: plane: Don't support active planes with CRTC disabled
It's unnecessary to support active planes with relevant CRTC being disabled,
because we cannot see the planes on the screen. Let's reject the case
in the atomic check stage explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK15951-2 arm:dts:imx8qm - Fix HDMI clocks
Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
MLK-15952-1 imx8qm: FIX HDMI clocks
The HDMI irqsteer incorrectly assumed that the HDMI bus clock will
be enabled automatically by the SCFW when HDMI SS is powered up.
Fix HDMI clocks so that the HDMI IPG clock is enabled when required.
Also fix all the LPCG addresses by HDMI clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
MLK-15048-2: video: Add proper config dependencies
Currently, if setting MXC_IPU to 'no' leads to a chain of build crashes.
This happens due to lack of proper config dependencies.
This patch fixes the following interdependencies:
- framebuffer sync panel (FB_MXC_SYNC_PANEL)
- should depend on IPU v3 (MXC_IPU_V3)
- ADV7535 MIPI-to-HDMI converter (FB_MXC_ADV7535)
- should depend on MIPI DSI (FB_MXC_MIPI_DSI)
- framebuffer MXS LCD controller (FB_MXS)
- should depend on framebuffer syn...
MLK-15048-1: media: v4l: capture: Move mxc/subdev/ drivers to mxc/capture
All drivers in mxc/subdev are capture devices, so move them to their
rightful place, in mxc/capture to avoid confusion.
Two of the drivers, ov5640 and ov5640_mipi are in both locations, having
the same configs: CONFIG_MXC_CAMERA_OV5640 and CONFIG_MXC_CAMERA_OV5640_MIPI.
After moving all to mxc/capture/ directory, add a _v2 suffix to those
drivers moved from mxc/subdev to allow a clean compile process. As a next
step, ...
MLK-15962: pxp-v3: fix pxp operation timeout issue
PxP block on imx6sll, imx6ull is different with imx7d, the node
path_ctrl should be different. So add path_ctrl for 6sll, 6ull.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
MLK-15937-4: ASoC: fsl_spdif: Use DMA workaround for SPDIF
Similar with commit 2f756e7aa88407 ("MLK-15004-4: ASoC: fsl_esai: esai
workaround for imx8qxp Rev1") this is needed because of a hardware
issue where SPDIF DMA request signal is active low but the DMA
input is active high.
The workaround uses GPT to convert DMA request signal to EDMA.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-15937-3: ARM64: dts: qxp: Add support for SPDIF
Instantiate sound-spdif node and add pinmux.
Connection on debug board is:
* SPDIF_OUT: SEAF_B_G39
* SPDIF_RX: SEAF_B_G38
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-15960-6: ARM64: dts: add power domain for audio clocks
The mclk_out clock is used as codec's mclk, so need to add
its power domain to codec node.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15960-5: ASoC: fsl_esai: refine pm runtime function
In imx8qm/imx8qxp, the power domain of IP is enabled when
pm_runtime_get_sync() is called, and disabled when pm_runtime
_put_sync() is called. when power domain is disabled, the value
of registers will lost, so we need to use the regcache_sync()
to restore the registers in fsl_esai_runtime_resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15960-4: ASoC: fsl_asrc: refine pm runtime function
In imx8qm/imx8qxp, the power domain of IP is enabled when
pm_runtime_get_sync() is called, and disabled when pm_runtime
_put_sync() is called. when power domain is disabled, the value
of registers will lost, so we need to use the regcache_sync()
to restore the registers in fsl_asrc_runtime_resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15960-3: ASoC: fsl_spdif: refine pm runtime function
In imx8qm/imx8qxp, the power domain of IP is enabled when
pm_runtime_get_sync() is called, and disabled when pm_runtime
_put_sync() is called. when power domain is disabled, the value
of registers will lost, so we need to use the regcache_sync()
to restore the registers in fsl_spdif_runtime_resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15960-2: ASoC: fsl_sai: refine the pm runtime function
In imx8qm/imx8qxp, the power domain of IP is enabled when
pm_runtime_get_sync() is called, and disabled when pm_runtime
_put_sync() is called. when power domain is disabled, the value
of registers will lost, so we need to use the regcache_sync()
to restore the registers in fsl_sai_runtime_resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15960-1: ASoC: fsl_sai: update fifo_depth for different platform
The fifo_depth is changed to 64 in imx8qm/imx8qxp, in imx8mq, the
fifo_depth is 128. which is mentioned in their ADD.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-15949-4 mmc: sdhci-esdhc-imx: restore the per_clk rate in PM_RUNTIME
When pm_runtime_suspend is run, a call to SCFW power off the SS in
which the resource resides is made. The SCFW can power off the SS
if no other resource in active in tha SS. If so, all state associated
with all the resources within the SS that is powered off is lost,
this includes the clock rates, clock state etc. When pm_runtime_resume
is called, the SS associated with that resource is powered up. But
the clocks are l...
MLK-15350 ARM64: dts: fsl-imx8mq-evk: add SD3.0 support
Add SD3.0 and eMMC HS400 support for imx8mq-evk.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
MLK-14765: Enable DCP SHA workaround on all platforms
Remove variant restriction for DCP SHA workaround. All integrations of
DCP seem affected.
Signed-off-by: Radu Solea <radu.solea@nxp.com>
MGS-3083 [#imx-662] fix gpu kernel build error with kasan config
remove _eventRecord and _commandBufferObject instrances, use stack to avoid below error:
hal/kernel/gc_hal_kernel_command.c: In function gckCOMMAND_Commit:
hal/kernel/gc_hal_kernel_command.c:2718:1:
error: the frame size of 2288 bytes is larger than 2048 bytes [-Werror=frame-larger-than=]
Date: Jul 13, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
