MLK-16045: pxp: add lut function in pxp data flow path
When do epdc colormap test, the epdc need pxp lut function. But
if the data flow through mux0->mux1...or mux0->mux2..., the pxp
can not trigger interrupt but mux0->mux3... can. This issue only
occures on imx7d, so I set a constant data path when using lut function.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
MLK-16068 printk: use console_trylock() in console_cpu_notify()
There is no need to always call blocking console_lock() in
console_cpu_notify(), it's quite possible that console_sem can
be locked by other CPU on the system, either already printing
or soon to begin printing the messages. console_lock() in this
case can simply block CPU hotplug for unknown period of time
(console_unlock() is time unbound). Not that hotplug is very
fast, but still, with other CPUs being online and doing
printk(...
MLK-16055 arm64: dts: freescale: imx8mq: enable power domain support
Assign i.MX8MQ power domain id to each module to enable
power domain control for runtime power management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK16061 imx8qm/imx8qxp: Add support allowing devices to enter into low
power mode during runtime suspend and idle.
On imx8qm/imx8qx, when devices enter into runtime suspend/idle,
the resource associated with the device will be enter a low power
state (as defined by SCFW). None of the state or clocks will be lost
in this mode.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
MLK-16064 arm64: dts: imx8qxp: force enet1 use PHY clock delay on lpddr4 arm2 board
Currently enet1 use MAC clock delay, there have packet error
in 100Mbps mode, no packet error in Gbps mode. Still use PHY
clock delay instead of MAC that 100Mbps mode has better timing
and no frame error.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16063-2 arm64: dts: add new dts file for imx8qxp mlb
add new dts file to support imx8qxp mlb due to pin conflict.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-16063-1 arm64: dts: disable mlb in default dts
mlb has pin confict with ESAI. So this patch disable mlb in dts.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
MLK-15132-8: Enable Hantro decoder on i.MX8MQ
Implement runtime PM, disable power/clk when vpu is not used
Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
MLK-16060: mtd: fsl-quadspi: fix the unalignment issue for qspi
ARM64 platforms may access QSPI from non-64-bit-aligned address which
causes unalignment fault. Fixed the issue for AHB reading.
Signed-off-by: Han Xu <han.xu@nxp.com>
usb: xhci: fix spinlock recursion for USB2 test mode
Both xhci_hub_control and xhci_disable_slot tries to hold spinlock, the
spinlock recursion occurs when enters USB2 test mode. Fix it by unlock
spinlock before calling xhci_disable_slot.
Cc: <stable@vger.kernel.org>
Fixes: 0f1d832ed1fb ("usb: xhci: Add port test modes support for usb2")
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linux...
xhci: use correct flags for spin_lock_irqrestore() when setting port power
commit a6ff6cbf1fab ("usb: xhci: Add helper function xhci_set_power_on().")
created a helper to control port power that needs to be called with
xhci->lock held and interrupts disabled.
It released the lock with spin_unlock_irqrestore using a new zero flag
variable instead of the original flag from spin_lock_irqsave.
This regression triggered a static checker warning about bogus flags, and
a null pointer dereference on...
usb: xhci: Add port test modes support for usb2.
For usb2 ports, the port test mode Test_J_State, Test_K_State,
Test_Packet, Test_SE0_NAK and Test_Force_En can be enabled
as described in usb2 spec.
USB2 test mode is a required hardware feature for system integrators
validating their hardware according to USB spec, regarding signal
strength and stuff. It is purely a hardware test feature.
Usually you need an oscilloscope and have to enable those test modes on
the hardware. This will send so...
usb: xhci: Expose xhci_start() function.
Change the visability of xhci_start() so that it
can be used when enabling test mode.
Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
usb: xhci: Add helper function xhci_disable_slot().
Refactoring slot disable related code into a helper
function xhci_disable_slot() which can be used when
enabling test mode.
Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
usb: xhci: Add helper function xhci_set_power_on().
Refactoring port power on/off related code into
a helper function xhci_set_power_on() which can
be reused when enabling test mode.
[set port state to neutral before writing port power -Mathias]
Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
MLK-15305-2: dma: imx-sdma: force to load context in sdma_config
Force to load context in sdma_config whatever context loaded or not,
since some configuration may change when the upper driver call sdma_config
such as bus width.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit ee8930b657af0c9ce2cfb1a521530c7d31016675)
MLK-16044 clk: imx: correct i.mx8mq qspi/nand clock name
i.MX8MQ QSPI and NAND's pre and post div clock
use incorrect parent name, correct them.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-16037: ARM64: dts: switch to use DMA.I2C0 instead HDMI.I2C0
Use the DMA.I2C0 instead HDMI.I2C0, they share same hardware pin
in imx8qm, then the HDMI power domain will not be enabled when
audio codec is working.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
MLK-16036 drm/imx: ldb: Avoid early return when getting aux PHY in dual mode
In dual mode, we return too early from ->bind when we get
the auxiliary channel's PHY. This causes we miss the logics
to set driver data, get ldb alias id and initialize pixel
link(if necessary). This patch fixes the issue here by
tweaking the driver logic to do component binding properly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-15343-3 PCI: imx: enable the DBI_RO_WR_EN of PCIEB
The DBI_RO_WR_EN of PCIEB should be asserted,
otherwise the CLASS_DEVICE can't be configured
correctly, then PCIEB RC doesn't work at all.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-15343-2 clk: imx8qm: correct the PD of PCIEB PHY CLK
Correct the PD of the PCIEB PHY CLK.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-15343-1 ARM: imx: enable pcieb on imx8qm
Based on base board, enable pcieb lane1, enlarge
the CFG mapping space.
HSIO configuration is 1 lane PCIEA, 1 lane PCIEB and SATA.
PHY configurations:
PHY_X2_0 <------> PCIEA 1 lane
PHY_X2_1 <------> PCIEB 1 lane
PHY_X1 <------> SATA
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-16020 drivers: soc: imx8: fill in machine field
As for imx6/7, read the 'model' field from device tree and fill in the
machine soc field.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
MLK-16038 ARM: dts: fsl-imx8mq-evk: improve the usdhc I/O drive strength
Some normal high-speed SD card may meet some CRC error on imx8mq-evk
board, so improve the default usdhc I/O drive strength to fix this.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
MLK-15132-7 : Enable Hantro decoder on i.MX8MQ
Refine clk/power operation
Adjust print level to reduce some unnecessary print info
Removing some redundant codes in bring up stage
Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
MLK-16025 ARM64: defconfig: enable xen backend blkdev
This provides a kernel dom0 based blkdev backend for domUs (raw disk)
and avoids the need to run qemu in dom0 as a backend for blkdev.
Signed-off-by: Octavian Purdila <octavian.purdila@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
MLK-16030-2 soc: imx: gpc: add power domain names
Add power domain names for i.MX8MQ, currently only
11 power domains support runtime ON/OFF.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-16030-1 arm64: dts: freescale: imx8mq: reduce power domain number
Reduce i.MX8MQ power domain number because some power
domains can NOT support runtime ON/OFF.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
MLK-16006: Revert "ARM: dts: imx6sx-sdb: Change audio PLL frequency for SSI"
This reverts commit d7d6f210522188 ("ARM: dts: imx6sx-sdb: Change audio
PLL frequency for SSI") because it breaks MQS.
MQS uses IMX6SX_CLK_SAI1 as master clock and it requires mclk rate to be
24576000. No other rate is supported.
Anyhow, due to change to fix MLK-14865 sai1 clk is changed to 36864000.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-16010: ASoc: fsl: support 32-bit application for hifi4
add cases to support 32-bit application for hifi4 when
kernel is running on 64-bit cpu mode.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
MLK-16023-05 arm64: dts: imx8qm/qxp: enable enet MAC delayed clocks
Since i.MX8QM/QXP ENET version add new feature that support delayed
clock for rxc/txc, then enable the feature on imx8qm/qxp arm2 boards.
Only enable i.MX8QM/QXP ARM2 board port0 delayed clock, port1 still
use PHY delayed clock. i.MX8QXP MEK board also use PHY delayed clock,
once get board then enable the port1 and verify MAC delayed clock in
MEK board.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16023-04 arm64: dts: imx8mq: clean up the enet compatible string
Since i.MX8MQ ENET is the same as i.MX6SX ENET version and don't
support new features added in i.MX8QM/QXP. So remove "fsl,imx8qm-fec"
compatible string.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16023-03: net: fec: add MAC delayed clock feature support
i.MX8QM/QXP ENET IP version add new feture to generate delayed TXC/RXC
as an alternative option to make sure it can work well with various PHYs,
which also is useful for MAC-to-MAC case. Add the new feature support.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16023-02: clk: imx8qm/qxp: correct the enetn_tx_2x_clk clock source
Correct the enetn_tx_2x_clk clock source to get the correct clk tree.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16023-01 net: phy: at803x: cleared the txc/rxc clk delay enable bits
RXC clock delayed bit is enabled in HW reset in default, and
to avoid uboot set RXC/TXC clk delayed bits, it should clear
these bits firstly.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16022 net: fec: get mac address from fuse
i.MX8QM/QXP MAC address only can be program by SCU, and A core
read fuse enet MAC address by sc APIs interface. i.MX8mScale is
inherited from i.MX7D, can directly read fuse in A-core.
Add i.MX8QM/QXP/MQ ENET MAC address check from fuse.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MLK-16015-8 gpu: imx: dpu: common: Initialize pixel link with correct settings
The pixel link configurations are broken into pieces in other drivers to
meet a recommended configuration sequence from the design team. So, let's
rename the function name of dpu_pixel_link_config() to dpu_pixel_link_init
and disable/invalidate pixel link as an initial status.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-7 gpu: imx: dpu: common: Make dpu_pixel_link_config() return void
This patch makes dpu_pixel_link_config() return void, since no one is
checking the return value and actually even if any of the SCU operations
inside this function fails we can do nothing about it.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-6 drm/imx: ldb: Add pixel link validate/invalidate logics
To enable or disable a display safely, we need to validate pixel link
after the relevant ldb channel is enabled and invalidate pixel link
before the channel is disabled. These operations are recommended
by the design team.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16015-5 drm/imx: ldb: Specify pixel link quirks to be initialization related
This patch specifies the existing pixel link quirks is initialization related.
This may help us distinguish between the pixel link quirks and another one
up-coming which is validation and invalidation related.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
