drm/edid: detect SCDC support in HF-VSDB
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info.
This structure will be used to save and indicate if sink
supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to
reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it
in scdc structure
- If SCDC is present, checks if sink is capable of generating
...
drm/edid: check for HF-VSDB block
This patch implements a small function that finds if a
given CEA db is hdmi-forum vendor specific data block
or not.
V2: Rebase.
V3: Added R-B from Jose.
V4: Rebase
V5: Rebase
V6: Rebase
V7: Rebase
V8: Rebase
V9: Rebase
V10: Rebase
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwo...
drm: Add SCDC helpers
SCDC is a mechanism defined in the HDMI 2.0 specification that allows
the source and sink devices to communicate.
This commit introduces helpers to access the SCDC and provides the
symbolic names for the various registers defined in the specification.
V2: Rebase.
V3: Added R-B from Jose.
V4: Rebase
V5: Addressed review comments from Ville
- Handle the I2c return values in a better way (dp_dual_mode)
- Make the macros for SCDC Major/Minor more readable, by adding
...
drm: Implement HDR source metadata set and get property handling
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm: Make drm_atomic_replace_property_blob_from_id() more generic
Change drm_atomic_replace_property_blob_from_id()'s first parameter
from drm_crtc to drm_device, so that the function can be used for other
drm_mode_objects too.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/851b8504c7f294a10645ba6f6d391ac9764068b7.1492768073.gi...
drm: Add a new connector atomic property for link status
At the time userspace does setcrtc, we've already promised the mode
would work. The promise is based on the theoretical capabilities of
the link, but it's possible we can't reach this in practice. The DP
spec describes how the link should be reduced, but we can't reduce
the link below the requirements of the mode. Black screen follows.
One idea would be to have setcrtc return a failure. However, it
already should not fail as the atomi...
drm: Add HDR capabilty field to plane structure
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm: Parse HDR metadata info from EDID
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm: Add CEA extended tag blocks and HDR bitfield macros
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm: Add HDR source metadata property
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
MLK-15071: ASoC: fsl: imx-ak5558: Fix clk for 384KHz and 786KHz
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When recording at 786Khz with current multiplier
MCLK = 24576000, requested freq 24576000 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 55a68a65bcf719677bb6a...
MLK-17620-2: ASoC: imx-cdnhdmi: switch to generic hdmi codec
switch to generic hdmi codec, which provide the api for get
the edid information.
Add snd controls which is the interface for user to query
the HDMI capibility. ( channels, rates, formats)
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 8b0d8a3f156fc1b7c1bc87f484b8905d1a41e209)
MLK-17459-4: drm: imx: dcss: fix weston
This patch fixes an issue introduced by the cropping patches which made
weston look bad. That's because use_dtrc flag was enabled if modifiers
were present. However, graphics plane can have modifiers too. This patch
adds an extra check.
Also, remove an unnecessary debug message.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17459-3: drm: imx: dcss: fixes for compressed format cropping
Cropping of compressed formats seems problematic and we cannot up-align
in this case. For compressed formats we need to down-align both the
width and height.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17459-2: drm: imx: dcss: add cropping functionality and fix odd resolutions
This patch fixes playback for movies with unaligned widths/heights and
adds cropping functionality for tiled formats. Untiled formats will not
have this feature as cropping is a DTRC function.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17459-1: drm: imx: dcss: change ctxld irq handling
To remove any possible latencies introduced by scheduling the bottom
half interrupt handler, do everything in the top half handler and get
rid of the IRQ worker thread handler. Also, that needs all mutexes
changed to spinlocks since mutexes can sleep.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MGS-3655: gpu-viv: integrate 6.2.4.p1 official release
update gpu kernel version with 6.2.4.p1 official release.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit 54d3cca04b8086aa7eb3bc8cf6077e8abedde6bd)
MLK-17600: ASoC: imx-ak5558: Set MCLK as a function of fs
MCLK frequency is determined based on LRCK frequency, according
to the operation mode. Because AK5558 runs in Auto Mode, we use
table 5 from datasheet to set the correct MCLK.
Multiplier must be set twice as value shown in RM because SAI
MCLK must be at least double the BCLK.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Cosmin Samoila <cosmin.samoila@nxp.com>
(cherry picked from commit 7b503a2b868ed4cdb43ce43755...
MLK-17590-02 driver: soc: imx: update the busfreq flow on imx8mq
Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.
The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit ff82e...
MLK-17590-01 driver: clk: imx: update the clk flag of pll
Add CLK_GET_RATE_NOCACHE and CLK_SET_RATE_GATE for sscg pll.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 762d4614b080b10155d0fc88cfe1fd477c3e5643)
MLK-17509: ASoC: imx-ak4458: Set MCLK freq as a function of FS
According to AK4458 RM the MCLK freq need to be set
externaly as function of LRCK frequency. Notice that
multiplier is twice the value shown in RM since SAI
MCLK must be at least double the BCLK.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 5609d20844eb6172bea19d0d894f36d5293f4fb5)
MLK-17552-2 PCI: imx: enable imx pcie ep dma
Enable the imx pcie ep dma in the pcie ep rc
validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit c72ab4303dbb242eb7ae0c2a5e20ac130addcf18)
MLK-17552-1 arm: dts: add the dma int for imx pcie ep
Add the dma int for the the imx pcie ep mode for
the controllers that has the dma capability.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit 5e76cceda3375ee760e4ca92ebd1c710fc1128b2)
MLK-17528-4: ASoC: imx-ak4497: set MCLK freq as function of FS
According to AK4497 RM the MCLK freq need to be set
externaly as function of LRCK frequency.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit e152bb541d2cd3c76d1a788d921d00ad7941ddef)
MLK-17528-3: ASoC: fsl_sai: Set clock rate in "set_sysclk" API
Set the requested clock rate in "set_sysclk" for specified clock id.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit f4c174362485db0079c36f1a8dd9973881de4ae9)
MLK-17528-2: ASoC: imx_pdm: Use FSL_SAI_CLK_BIT to signal the proper clock id
The current implementation suggest that MAST1 frequency is to be changed,
which is wrong. Use FSL_SAI_CLK_BIT clock id instead of FSL_SAI_CLK_MAST1
in order to make the code more intuitive and to signal proper
clk_id to SAI.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit b5440fdf2629...
MLK-17528-1: ASoC: fsl_sai: Introduce FSL_SAI_CLK_BIT clock id
Introduce FSL_SAI_CLK_BIT clock id in order to distinguish
the bit clock and master clocks in "set_sysclk" API.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 75678bd523439de84eec00fdae1e4f9d11b9fcad)
MLK-17555 ARM64: defconfig: add usb video support
Add usb video support by build it as module.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
(cherry picked from commit fb7e2a86d23316976ccd65a339cf7d8790ad7828)
MLK-17566: ASoC: fsl_sai: fix register definition
The register definition is not completed for SAI support
8 transmit data register and 8 receive data register.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 9a376da8b90f9562f833896542d8cc615d69a8e4)
MLK-17253-3: dtb: Fix the size of SM available in imx8mq dtsi
The Secure Memory contain 8 pages of 4k byte but the
node was only expressing half this space.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
MLK-17253-2: crypto: caam: Use correct memory function for Secure Memory
The Secure Memory is a hardware memory whose address was retrieved using
of_iomap, hence the memory manipulation shall use the set of functions:
memset_io/memcpy_fromio/memcpy_toio in order to works correctly.
Not using these functions can result in kernel panic.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
MLK-17253-1: crypto: caam: Fix computation of SM pages addresses
The computation of the base address of the physical and virtual
need to be the same depending on the architecture.
The addresses are computed using a pointer on u8 so the additions
always works as expected.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
MLK-17515-2: ARM64: dts: move the pdn gpio to sound card node
move the pdn gpio to sound card node for ak4458
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Cosmin Samoila <cosmin.samoila@nxp.com>
(cherry picked from commit 54d71caaa6cfb11bfa86170b3ae81b6e07737f8d)
MLK-17515-1: ASoC: imx-ak4458: add pdn gpio for machine driver
There is two ak4458 codecs which share some pdn gpio. If assign
the pdn gpio to one codec, will cause the another codec error:
ak4458 1-0012: Unable to sync registers 0x0-0x0. -6
The reason is that if the codec driver is trying to do regcache_sync,
but another codec is resetting the pdn gpio in same time, the
regcache_sync will fail.
So Move the pdn gpio to machine driver, machine driver will
control this gpio for two codecs.
...
MLK-17517: ARM64: dts: imx8mq-evk: Fix record for more than two channels
SAI5_RXDn must be muxed to RX_DATAn. For n = {1, 2, 3}
this mapping was not correctly done so only channels
recorded from data line 0 were seen in .wav capture.
Suggested-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviwed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 66f2533b447ae85a95f66cb79f8c7cfc970e3d4e)
MLK-17507: ASoC: ak4458: add return value for ak4458_codec_probe
There is ak4458 audio card even no audio board connected, which
is caused by there is no error return value even the i2c access
failed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 22fa7070b753dc2ec9d5558463d3f5f89d02f257)
MLK-17523 drm/imx: dcss: do dec400d shadow trigger only for primary plane
Since only primary plane has DEC400D attached to it, the
shadow register trigger for DEC400D is only necessary to
be done for primary plane update.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit f3834c73366f985fef6c1fdaaa129dfceb6151cb)
MLK-17485: ASoC: fsl_sai: Specify supported rate_min and rate_max
Because fsl_sai_dai rates doesn't have a specific set of
rate values (.rates = SNDRV_PCM_RATE_KNOT) we need to provide
rate_min and rate_max otherwise functions trying to get
supported parameters will get confused and return an error.
Fixes: 1b6f0496e013 ("MLK-17428-8: ASoC: fsl_sai: support 768KHz sample rate")
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry pick...
MLK-17516: ASoC: fsl: amix: refine the error handling
The "snd_pcm_hw_constraint_minmax" call may return a positive
non-error integer so that the subsequent "snd_pcm_hw_constraint_mask64"
call is never invoked, thus the formats are never enforced.
Fix the error handling so that only negative results are considered.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 63cb54d845564172a23fa23e3f7d982de448ecd9)
MLK-17470-2: ASoC: ak4497: review get/set_dsdsel
With commit 69201427e188 ("MLK-17470: ASoC: ak4497: automatically select dsdsel
in driver") the "ak4497_priv.nDSDSel" field might not reflect the real dsdsel
option. In order to simplify the approach and avoid future inconsistencies the
field is removed and dsdsel option is read/stored directly to/from codec
registers. Aside of this a missing dsdsel option for 22.5792MHz is introduced
in "ak4497_set_dsdsel" method, now this method being fully ...
MLK-17514: drm/imx: dcss: directly bypass dec400d when no modifier present
When no modifier present, the 'fb->modifier[0]' may contain
undefined value. So it cannot be used to decide whether the
DEC400D should be set to bypass or not in this case.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 25b9ab8e8120fd6eb048e52e14d8d81b0b41ca85)
MLK-17492 drm/imx: dec400d: set read config to '0x0' when bypass dec400d
When the DEC400D is set to bypass mode from decompressed mode,
the read config should be set to disable compression along with
the control register. Otherwise, the DEC400D cannot really leave
the decompressed mode. And the value '0x0' is suitable to be set
to read config register in this case.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 11d31a565dca268f64100735ac2a3ab112799171)
MLK-17490-2 drm/imx: dec400d: fix wrong path to define 'dcss_dec400d_write()'
The macro 'USE_CTXLD' usage in function 'dcss_dec400d_write()'
is opposite to the real defintion path.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 5e0a3057c7fefd215c2507f7d858e8f9f1cbf74f)
MLK-17490-1 drm/imx: dec400d: fix incorrect register base passed to context loader
The register base of DEC400D which is passed to context loader
should be the physical address but not the ioremaped virtual
address.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 6d5bc0a9bfc73f39bf03affb3fce9eebdaa71fc0)
MLK-17486 arm64: dts: imx8mq-evk-m4: Disable QSPI and SAI2 for M4
Since M4 will use QSPI and SAI2, disable the relevant nodes in M4
dedicated DTB.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 835a41dc2cd5f471af3ea6ef0e3d87922295a617)
MGS-3632-2: drm: imx: dcss: adjust DPR MAX_BYTES_PREQ depending on resolution
Current setting uses a 256 bytes/request for anything less than 1080p.
This works when DTRC is not involved. However, with DTRC, the
MAX_BYTES_PREQ needs to be fine tuned a little.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MGS-3632-1: drm: imx: dcss: adjust ratio when WR_SCL kicks in
Using WRSCL for downscaling ratios between 3 and 5 can lead to more
DDR bandwidth beeing used (~400MB/s).
Hence, use WR_SCL only for downscaling ratios from 5 to 7.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
