MLK-15071: ASoC: fsl: imx-ak4497: Fix clk for 384KHz and 786KHz
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When playing at 786Khz with current multiplier
MCLK = 22579200, requested freq 22579200 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 74168d9e1e02d27d1f737c146d7909601049f197)
MLK-17732-2: SM store: Support iMX8QX and iMX8QM
The iMX8 QX and QM have SECO/SCU enabled and the access
to SM registers is different as long as the addresses of
the pages.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit b4f1f3761d6e40996a19e4e6d26d7483d2f1661f)
MLK-17732-1: defconfig: imx8m: Enable SM keystore and test
We enable the SM keystore and its test by default to be
tested at the boot of the kernel.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit a32bfdc010dfbdce35a065c0ede19296f4523d7d)
MLK-17648-2: drm: imx: dcss: Load the HDR10 from header file
This commit allows one to select if a firmware file is used, for loading
the HDR10 tables, or a header. By default, this will be header file.
This is until a proper way of passing the file from bootloader is found.
Also, fix a minor bug which made parsing the tables over the actual data
limit.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 825755bb599fba99e8ed16caa3738b8f66c3448d)
MLK-17648-1: drm: imx: dcss: add HDR10 module tables
This commit adds HDR10 tables as a header. Using a FW file is
problematic since the tables need to be available immediately after
boot. After the rootfs is mounted, as is the case for loading a FW file,
it's already too late if some conversion tables are needed.
This usually happens if the output pipe is configured as YUV420.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit dfb6fa2943119c2b371809f3b3b04...
MLK-17739 tty: serial: imx: clear wakeup flag before enable wakeup interrupt
It is better to clear wakeup flag in status register before enable
wakeup interrupt bits, which can avoid system suspend fail during
devices no irq suspend stage.
Reviewed-by: Gao Pan <pandy.gao@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit e8e3a042847f7ca3b24103fdc7647f231a0b3cbf)
MLK-17734-2: ASoC: fsl: ak5558: Remove support for 192KHz in TDM mode
Using TDM256 mode (our only supported mode) in order to
support 192KHz we would need a MCLK of 192000 * 512 = 98304000.
But maximum frequency supported by the Audio PLL is 4.91 MHz.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 11aa41d02e69e6f23b28f0df4c74194703cb720b)
MLK-17734-1: ASoC: fsl: imx-ak5558: Fix TDM mode for 8kHz / 16Khz
In order for TDM to correctly work we need that MCLK and
BCLK to follow the values in Table 9.
Thus,
* TDM128: BCLK = 128fs, MCLK = 128-1024fs
* TDM256: BCLK = 256fs, MCLK = 256-1024fs
* TDM512: BCLK = 512fs, MCLK = 512-1024fs
We assume only support TDM256 for the moment.
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit 63d9fd2177a0199f0565...
MLK-17647: drm: imx: dcss: fix the flip_done timed out problem
The commit:
44c45128 - MLK-17634-1: drm: imx: dcss: send vblank event from ISR
made some changes related to vblank handling. However, it looks like
they were not robust enough and, sometimes, the flip events are not
sent. This happens only when playing videos over Weston.
This patch, effectively, reverts those changes.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 1319160b42390947864eb01e...
MLK-17689-3: arm64: dts: fsl-imx8mq-evk: Fix clocks for DCSS-RM67191
Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by the
DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17689-2: arm64: dts: fsl-imx8mq-evk: Fix clocks for DCSS-ADV7535
Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by
the DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
MLK-17569-1: hdp: fix channel swapping issue for hdmi audio
There is channel swapping issue for 4 channel and 8 channel audio.
After dump the register, found that SMPL2PKT_CNFG is not set
correctly, the reason is that F_NUM_OF_I2S_PORTS should be
F_NUM_OF_I2S_PORTS_S.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
(cherry picked from commit 0bb30f24474dfce7f4ad70343f5f39a645e4b407)
Sound: SoC: codecs: Put AK4458 codec in manual mode
We cannot both derive SAI BCLK for 384KHz-S32/768KHz-S16 and
respect the codec MCLK restrictions shown in AK4458 datasheet
Table 5, 6 and 7.
Since we can have same master clock for SAI and Codec in Manual
Mode, we've chosen to use it instead of Auto Mode.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 46a1f17da003feb8bcac6b3b1d1c24a84c988c06)
Sound: Soc: fsl: Set SAI Channel Mode to Output Mode
Transmit data pins will output zero when slots are masked or channels
are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
slots are masked or channels are disabled. When data pins are tri-stated,
there is noise on some channels when FS clock value is high and data is
read while fsclk is transitioning from high to low.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wa...
MLK-17645: drm: imx: dcss: fix DTRC start issue
The following commit:
af01350 - MLK-17634-18: drm: imx: dcss: optimize context loading and DDR
bus load
introduced a regression. During my attempts to fix various green screen
issues, I modified the DTRC start routine by enabling the other register
bank, not the current one.
Unfortunately, this was committed by mistake...
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 2a6b73acb9c6f3a307d9a2d286991f16e435...
MLK-17655: drm: imx: hdp: send HDR metadata when property is set
HDR metadata infoframe was sent only when doing a mode set. However,
kmssink is using the same device as Weston and mode setting messes up
with Weston's plane state.
This patch allows for the HDR metadata to be sent out to the sink when
the property is set. Hence, no need for a mode set.
Also, the older functionality allowed only for 4K@60 to be used for HDR.
However, HDR is not about resolution. This patch will also allow to...
MLK-17671-2: drm: imx: hdp: mscale: remove delay at the end of mode setting
Since DCSS was moved to use VIDEO2_PLL clock, HDMI phy clock is not used
anymore. Hence, this delay here is not necessary. It's been added inside
DCSS driver.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit aeff3bf78ced6e27a262c9022e658f57f5239c23)
MLK-17671-1: drm: imx: dcss: add a delay after changing the pixel clock
DCSS needs some time to stabilize after switching to a new pixel clock.
All interrupts will delayed till the clock stabilizes and we'll end up
getting warnings about VBLANK interrupt taking more than 50ms to arrive.
This patch adds a 500ms delay after switching to a new clock. This will
allow DCSS to stabilize before enabling CRTC and DTG channels.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked...
MLK-17626: drm: imx: dcss: fix "ctxld error" messages
The problem arised because of a combination of 2 commits:
Commit 1:
"2a70f32 - MLK-17232-2: drm: imx: dcss: ignore SB_PEND_DISP_ACTIVE
interrupt"
disabled the SB_PEND_DISP_ACTIVE interrupt because of a problem in SOC.
However, it did not remove the flag from CTXLD_IRQ_ERROR macro.
Commit 2:
"f0e3911 - MLK-17459-1: drm: imx: dcss: change ctxld irq handling"
moved the bottom half interrupt handling to top half. By doing that, the
top ...
MLK-17634-18: drm: imx: dcss: optimize context loading and DDR bus load
This will lower the amount of ctxld entries sent, if configuration has
not changed much. Also, disable channel 0 if alpha is 0 and global alpha
is used. This will lower the DDR load, depending on graphics channel
resolution.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-14: drm: imx: dcss: Add basic HDR10 support
This patch adds basic HDR10 support. However, full support depends on
subsequent patches.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-13: drm: imx: dcss: remove the dcss-tables header
The tables header is no longer necessary as dcss.fw file will be used
from now on to store LUT and CSC tables.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-12: drm: imx: hdp: Send HDR metadata to the sink
If the HDR metadata proprety is set, then the metadata will be sent
to the sink at the next mode set.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-11: drm: imx: dcss: make DCSS use VIDEO2_PLL2 clock
This clock is needed by HDR10 so this patch makes DCSS use VIDEO2_PLL2
for the rest of the resolutions as well.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-10: clk: imx8m: add support for 27MHz phy clock and fix pll2 round/set rate functions
The SSCG PLL2 is identical to PLL1, hence make the rounding/setting
functions reflect that.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
MLK-17634-6: drm: imx: dcss: add P010 drm format
This is 10-bit per channel YUV420 semi-planar.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
drm: add helper functions for YCBCR420 handling
This patch adds helper functions for YCBCR 420 handling.
These functions do:
- check if a given video mode is YCBCR 420 only mode.
- check if a given video mode is YCBCR 420 also mode.
V2: Added YCBCR functions as helpers in DRM layer, instead of
keeping it in I915 layer.
V3: Added handling for YCBCR-420 only modes too.
V4: EXPORT_SYMBOL(drm_find_hdmi_output_type)
V5: Addressed review comments from Danvet:
- %s/drm_find_hdmi_output_typ...
drm/edid: parse ycbcr 420 deep color information
CEA-861-F spec adds ycbcr420 deep color support information
in hf-vsdb block. This patch extends the existing hf-vsdb parsing
function by adding parsing of ycbcr420 deep color support from the
EDID and adding it into display information stored.
V2: Rebase
V3: Rebase
V4: Moved definition of y420_dc_modes into this patch, where its used
(Ville)
V5: Optimize function, if(conditions) not reqd (Ville)
V6: Rebase
V7: Rebase
Cc: Ville Syrjälä <...
drm/edid: parse sink information before CEA blocks
CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
This block contains a map of indexes of CEA modes, which can
support YCBCR 420 output also. To avoid multiple parsing of same
CEA block, let's parse the sink information and get this map, before
parsing CEA modes.
This patch moves the call to drm_add_display_info function, before the
mode parsing block.
V4: Introduced new patch in the series
V5: Move this patch before 4:2:0 par...
drm/edid: parse YCBCR420 videomodes from EDID
HDMI 2.0 spec adds support for YCBCR420 sub-sampled output.
CEA-861-F adds two new blocks in EDID's CEA extension blocks,
to provide information about sink's YCBCR420 output capabilities.
These blocks are:
- YCBCR420vdb(YCBCR 420 video data block):
This block contains VICs of video modes, which can be sopported only
in YCBCR420 output mode (Not in RGB/YCBCR444/422. Its like a normal
SVD block, valid for YCBCR420 modes only.
- YCBCR420cmdb(YCBC...
drm/edid: cleanup patch for CEA extended-tag macro
CEA-861-F introduces extended tag codes for EDID extension blocks,
which indicates the actual type of the data block. The code for
using exteded tag is 0x7, whereas in the existing code, the
corresponding macro is named as "VIDEO_CAPABILITY_BLOCK"
This patch renames the macro and usages from "VIDEO_CAPABILITY_BLOCK"
to "USE_EXTENDED_TAG"
V2: Add extended tag code check for video capabilitiy block (ville)
V3: Ville:
- Use suggested names f...
drm: add helper to validate YCBCR420 modes
YCBCR420 modes are supported only on HDMI 2.0 capable sources.
This patch adds:
- A drm helper to validate YCBCR420-only mode on a particular
connector. This function will help pruning the YCBCR420-only
modes from the connector's modelist.
- A bool variable (ycbcr_420_allowed) in the drm connector structure.
While handling the EDID from HDMI 2.0 sinks, its important to know
if the source is capable of handling YCBCR420 output, so that no
Y...
drm: Enable HDR infoframe support
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm: Parse Colorimetry data block from EDID
EA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
drm/edid: detect SCDC support in HF-VSDB
This patch does following:
- Adds a new structure (drm_hdmi_info) in drm_display_info.
This structure will be used to save and indicate if sink
supports advanced HDMI 2.0 features
- Adds another structure drm_scdc within drm_hdmi_info, to
reflect scdc support and capabilities in connected HDMI 2.0 sink.
- Checks the HF-VSDB block for presence of SCDC, and marks it
in scdc structure
- If SCDC is present, checks if sink is capable of generating
...
