MLK-16595 rpmsg: imx: enable multi-core string demo
Because that there are two M4 cores on iMX8QM.
Enable the multi-core string echo support.
BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-16609: arm64: dts: support flexspi on i.MX8QM MEK
add device tree node to support flexspi on i.MX8QM MEK board.
BuildInfo:
- SCFW 9e9f6ec6, IMX-MKIMAGE e1b3bc76, ATF 0
- U-Boot 2017.03-00072-gfdcf70a
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16601: ARM64: dts: imx8mq: support spdif on mscale evk
Enable the spdif1 on mscale evk, the tx is tested with fly wire to
MX51EXP (sch-26109) board, rx is not tested(waiting the audio board).
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
MLK-16600 gpu: imx: dpu: common: Initialize pixel link in resume() only if necessary
We should initialize pixel link in resume() for DPUv2 which
has pixel link quirks, but not for DPUv1 which hasn't the quirks.
Fixes: 0d7fa2aa1a9f ("MLK-16581-6 gpu: imx: dpu: Add system power management support")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16586-3 rpmsg: imx: enable multi-core rpmsg
- Init multi-core mu power and clk.
- enable the multi-core rpmsg support
BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Tested-by: Andy Duan <fugang.duan@nxp.com>
MLK-16586-2 ARM64: dts: imx: enable multi-core rpmsg support
Because there are two m4 cores on imx8qm,
enable imx8qm multi-core rpmsg support
BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Andy Duan <fugang.duan@nxp.com>
Tested-by: Andy Duan <fugang.duan@nxp.com>
MLK16557 soc:imx8qm/imx8qx - Resources can request low power idle mode only when runtime-pm is enabled.
Some drivers use runtime PM callbacks during suspend/resume also and this
in turn results in SCFW calls requesting the resource to enter
low power idle instead OFF state.
This patch fixes this issue by ensuring that low power IDLE request is only
valid when runtime PM is enabled. Runtime PM is disabled when the system is
entering suspend state.
BuildInfo: SCFW 7a725203, IMX-MKIMAGE ee6adf...
MGS-2717-2 [#ccc] Error message printed on board that didn't support gpu govern when rmmod galcore
When rmmod galcore.ko on boards that didn't support gpu govern,
some error message will be printed on console, do something to prevent this.
Date: Oct 16, 2017
Signed-off-by: Yuchou Ganyuchou.gan@nxp.com
Reviewed-by: Xianzhong xianzhong.li@nxp.com
Reviewed-by: Prabhu Sundararaj prabhu.sundararaj@nxp.com
MLK-16581-7 drm/imx: ldb: Add system power management support
This patch adds system power management support for imx-ldb drm driver
by proper PHY power/exit/init handling where necessary and pixel link
re-initialization in the resume operation. The driver depends on the
imx-drm core driver to handle ldb bridge power management operations.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-6 gpu: imx: dpu: Add system power management support
The dpu core driver currently depends on the client drivers
to do suspend operations to leave dpu a cleaned up state
machine status before the system enters sleep mode. When the
system resumes, the dpu core driver resume operation will
re-initialize the machine state by enabling intsteer lines,
re-initializing pixel links and re-initializing dpu sub-units.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-5 gpu: imx: dpu: common: Add helper dpu_intsteer_enable_lines() support
This patch adds helper dpu_intsteer_enable_lines() support so that
users may enable intsteer lines with one function call.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-4 gpu: imx: framegen: Get pll & pixel clock rates before setting their rates
Due to i.MX8 clock issue, we need to get pll and pixel clock rates
before setting their rates when system resumes back from PM sleep mode,
otherwise, we'll fail to set the clock rates. So, this is a workaround
and it can be removed when the clock issue is properly fixed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-3 drm/imx: ldb: Get bypass & pixel clock rates before setting their rates
Due to i.MX8 clock issue, we need to get bypass and pixel clock rates
before setting their rates when system resumes back from PM sleep mode,
otherwise, we'll fail to set the clock rates. So, this is a workaround
and it can be removed when the clock issue is properly fixed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-2 phy: mixel-lvds-combo: Get PHY clock rate before setting it's rate
Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16581-1 phy: mixel-lvds: Get PHY clock rate before setting it's rate
Due to i.MX8 clock issue, we need to get PHY clock rate
before setting it's rate when system resumes back from
PM sleep mode, otherwise, we'll fail to set the clock rate.
So, this is a workaround and it can be removed when
the clock issue is properly fixed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
drm: Take ownership of the dmabuf->obj when exporting
Currently the reference for the dmabuf->obj is incremented for the
dmabuf in drm_gem_prime_handle_to_fd() (at the high level userspace
interface), but is released in drm_gem_dmabuf_release() (the lowlevel
handler). Improve the symmetry of the dmabuf->obj ownership by acquiring
the reference in drm_gem_dmabuf_export(). This makes it easier to use
the prime functions directly.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet:...
MLK-16571-5: arm: dts: i.MX7ULP LPSPI IPG clock change
i.MX7ULP LPSPI also use both ipg/per clock for the module, which ipg
clock was not exposed. Add one dummy clock as ipg clock to make the
lpspi code neat and clear.
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16571-4: lpspi: support nor chip access from lpspi
i.MX8QM connects the AT45DB041E nor chip to lpspi, change the lpspi
driver to request irq before bitbang starts, add both ipg and per clock
for i.MX8QM and add gpio cs to keep the cs asserted during nor access.
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16571-3: arm64: dts: add i.MX8QM lpspi device node
add the lpspi device node and change the peripheral to nor chip.
i.MX8QM also need both ipg and per clock for this module.
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16571-2: arm64: defconfig: enable lpspi and dataflash
To support the AT45DB041E nor chip on i.MX8QM base board, enable both
lpspi and dataflash in defconfig
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16571-1: Kconfig: arm64: enable lpspi for MXC_ARM64
enable the lpspi config for arm64 in Kconfig
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao <pandy.gao@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16572: mtd: gpmi-nand: change the NAND omux setting
use the dqs and re pins rather than dqs_n/dqs_p re_n/re_p pins for NAND
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16585 net: fec: fixup: correct i.MX8QXP MAC address fuse mapping
i.MX8QXP has different fuse address with i.MX8QM, correct i.MX8QXP
MAC fuse word address.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
MGS-2717-2 [#ccc] GPU Scaling governor
Implement the gpu scaling governor so that you can switch the clock rate in user space like this:
echo "overdrive" > /sys/bus/platform/drivers/galcore/gpu_mode
echo "nominal" > /sys/bus/platform/drivers/galcore/gpu_mode
echo "underdrive" > /sys/bus/platform/drivers/galcore/gpu_mode
or cat /sys/bus/platform/drivers/galcore/gpu_mode to get the supported modes/frequency and current running mode.
Date: Oct 11, 2017
Signed-off-by: Yuchou Gan <yuchou.gan@nxp...
MLK-16573-1 arm64: dts: imx8qxp-mek: add pca6416 IO expander support
NXP pca6416 is compatible with TI tca6416.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
MLK-16559 flexcan: make MB mode be able to receive extend frame
By default Rx Mailbox filter’s IDE bit is always compared and RTR is
never compared despite mask bits which will result in MB can't receive
extend frames with random IDs. (CAN_CTRL2[EACEN] is 0)
Let's enables the comparison of both Rx Mailbox filter’s IDE and RTR bit
according to mask bits. Since mask bits are all set to 0 currently,
it makes MB can receive both standard and extend frames.
BuildInfo:
- SCFW d0458f9f, IMX-MKIM...
MLK-16546-2 soc: imx: pm-domains: support early power on resource after resume
On i.MX8QM/8QXP, for some resources which act as irq chip
etc., they need to be powered on earlier than device resume
phase, as they need to access registers, common power domain
resume is too late, so add syscore resume callback in pm
domain driver, for those resources with "early_power_on"
property set, they will be powered on at syscore resume phase,
by default, it supports 10 resources, and can be increased
if...
MLK-16546-1 ARM64: dts: freescale: imx8qxp: add early_power_on property
Introduce early_power_on property, for those power
domain nodes with this property set, power domain driver
will power them on at syscore resume phase, since some
resources need to be power on earlier than device resume
phase, like irq chip driver etc..
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
MLK-13946-7: ARM64: defconfig: add CONFIG_SND_SOC_IMX_CDNHDMI
Commit 3f16567eedabd3 ("MLK-16538-4: defconfig: Add hdmi/dp driver to
default kernel build") removed audio HDMI from defconfig.
Add it back after fix the compile issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-6: ARM64: dts: remove video-mode in hdmi audio node
according the new api, video-mode is not needed for hdmi audio, it is
replaced by protocol property.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-5: ARM64: dts: enable dp audio for imx8qm
Enable dp audio for imx8qm, define sai hdmi tx and rx node.
use property "procotol" to replace the "video-mode"
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-4: ASoC: imx-cdnhdmi: refine machine driver for api changes
Since commit 3f5780eb4520 ("MLK-16538-2: hdmi api: Relocate hdmi api
soure code") change the api. And hdmi video driver provide a new api
for hdmi audio. Machine driver need to be updated accrodingly
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-3: ASoC: fsl_sai: fix the xMR setting
When there is multi data line enabled, the xMR setting is
wrong if according to the channel number. which should
according to the slot number
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-2: hdp: add i2s clock for imx8qm hdmi audio
hdmi audio need to enable the i2s clock and i2s_bypass clock
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-13946-1: clk: imx8qm: fix the definition of HDMI I2S clock
The resource id of HDMI I2S clock is SC_R_HDMI_I2S, and SAI HDMITX
and HDMIRX clock need FUNCTION_NAME paremeter.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-16575 gpu: imx: dpu: fetcheco: Correct dpu->fe_priv[] access in dpu_fe_init()
The array size of dpu->fe_priv is only 4. We need to access the correct
entry of the array by comparing the id passed in dpu_fe_init() with
the entries in the fe_ids array instead of using the id directly.
This may avoid out-of-boundary array access on dpu->fe_priv.
Fixes: 936b978c44f3 ("MLK-16075-11 gpu: imx: dpu: Add basic fetcheco units support")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16574 gpu: imx: dpu: layerblend: Fix layerblend_shdldsel()
The shadow load selection field of layerblend is at bit[2:1].
Thus, we need to shift to left by one bit for the selection value.
Fixes: 4ec895ea31a2 ("MLK-15001-11 gpu: Move ipuv3 and dpu to imx folder")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
