Commits
Laurentiu Palcu committed 0804888cfe9
MLK-17634-10: clk: imx8m: add support for 27MHz phy clock and fix pll2 round/set rate functions The SSCG PLL2 is identical to PLL1, hence make the rounding/setting functions reflect that. Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>