MLK-16693-2: mipi_csi: fix null video name setting
Setting video device name before memset operation
lead to null value of vdev->name
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit d342872a4db74cdbbc955b0e5c73d3cd86b217be)
MLK-16692-2: mipi_csi: Add S_PARM and G_PARM ioctl
Add VIDIOC_S_PARM and VIDIOC_G_PARM ioctl to support
to get and set camera parameters
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 9ff408ace21f64d528f2abb37614889fe7a624fc)
MLK-16692-1: csi: Identify which camera really connect to interface
There maybe 0-4 cameras can connected to interface at
the same time. Add this ioctl to identify which camera
really connect to the interface.
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 785fbbd10c8a484b7f70488234c3a03e9aee9992)
MLK-16682 usb: cdns3: gadget: delete useless is_iso_flag
Since the runtime endpoint type is decided by device descriptors,
we delete useless is_iso_flag which is decided during the initialization.
It also fixed a bug the max_packet_size is determined wrongly for
high/full speed connection.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16727-4 ARM64: dts: fsl-imx8qxp-mek: change PD role as source only
At MEK hardware design, the PD is source only, so the software must
configure PTN5110 as source only, otherwise, there is an inrush higher
voltage at vbus when connects to PC due to EN_SRC is enabled at DRP
mode, and causes some PC are shut down.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter...
MLK-16727-3 usb: cdns3: force vbus status accordingly
Since the controller doesn't know vbus status well due to IC limitation,
it needs to force vbus status for controller when the connection and
disconnection occur.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
MLK-16727-2 Revert "MLK-16285-5 extcon: extcon-ptn5110: only sends EXTCON_USB_HOST event"
This reverts 'commit cca4c561e412 ("MLK-16285-5 extcon: extcon-ptn5110:
only sends EXTCON_USB_HOST event")'
Some controllers (eg, Cadence USB3) need to know vbus disconnection
status for its internal state machine, so we need Type-C chip to
send this event as well.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Acked-by: Li Jun <jun.li@nx...
MLK-16727-1 usb: cdns3: needs to handle disconnection at device mode
The IP has some issues to detect vbus status correctly, we have to
force vbus status accordingly, so we need a status to indicate
vbus disconnection, and add some code to let control know vbus
removal, in that case, the controller's state mechine can be correct.
In this commit, we increase one role 'CDNS3_ROLE_END' to for
this status.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.5...
MLK-16772 gpu: imx: dpu: cf: Add safety_stream_cf_color module parameter support
This patch adds safety_stream_cf_color module parameter support so that
users may set the default color generated by the constframe units(4 and 5)
of safety streams.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
MLK-16771 drm/imx: dpu: kms: Change to use a better KMS
This patch improves DPU KMS by the following means:
1) Wait for shadow registers being loaded in ->atomic_flush()
to make sure there is no intermediate register values being
loaded when doing atomic update.
2) Improve CRTC enablement/disablement sequences/configurations
according to spec.
3) Remove the FGDM__PRIM framegen display mode from ->mode_set_nofb()
and always use FGDM__SEC_ON_TOP mode so that we may prepare
for i...
MLK-16755 video: fbdev: mipi_dsi_northwest: fix a linker error when do 64bit div
Compiling the 64-bit integer direct division statement by
32-bit GCC compiler may trigger below linker error:
"
drivers/built-in.o: In function `mipi_dsi_enable':
core.c:(.text+0x2ad48): undefined reference to `__aeabi_uldivmod'
core.c:(.text+0x2ad60): undefined reference to `__aeabi_uldivmod'
core.c:(.text+0x2ada4): undefined reference to `__aeabi_uldivmod'
core.c:(.text+0x2ade8): undefined reference to `__aea...
MLK-16769-3: dma: mxs-dma: clean up the i.MX7D clock code
There is only one clock need to be handled after the clock code change
for i.MX7D. remove the redundant code.
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16769-1: clk: imx7d: create clocks behind rawnand clock gate
Merge community clock code change for i.MX7D.
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.
Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.
Signed-off-by: Han Xu ...
MLK-16742-1: dts: arm64: imx8qxp: Set proper compatible string
Set proper compatible string in order to trigger
proper handling of constrain_period_size.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-16760 soc: imx: support i.MX8MQ new revision SoC
On i.MX8MQ, the new revision SoC does NOT update the
revision info in ANATOP_DIGPROG register, to support
dynamic SOC id/revision detection, only reading info
from ANATOP_DIGPROG is not working now, change to read
SOC id/revision from ATF which is in secure world.
The ATF will read the ANATOP_DIGPROG as well as ROM
version to decide the SOC revision.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
MLK-16754 ARM64: dts: imx8qm: enable the smmu on sata
enable the smmu on sata
BuildInfo:
- SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-16697 staging: typec: tcpci: add notfication for device attach
Some usb device driver can't know the connect and disconnect to host
if the vbus is always on, if use typec we can rely on cc line status
to know that, so add a notification to let controller driver know
device attach and detach from host.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
MLK-16686-2 ARM64: dts: imx8mq: enable rpmsg on imx8mq
Enable rpmsg support on imx8mq platforms.
- To avoid the potenial confliction, reduce the allocation
scope of CMA.
- Reserved the 0xb800_0000 1Mbyte for RPMSG
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-16746 imx8mq: support m4
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
MLK-16706-4 video: fbdev: mipi_dsi_northwest: improve phy pll config
The MXL PLL uses the following function to generate
the output clock 'CLKOUT' based on the input 'CLKREF'
(which is the reference clock):
"
CLKOUT = CLKREF * CM / (CN * CO);
CM range is in [16, 255];
CN range is in [1, 16];
CO range is in {1, 2, 4, 8};
"
So the DSI driver needs to derive proper 'CM', 'CN'
and 'CO' to get the required 'CLKOUT' based on the
'CLKREF'. This commit provides a general method to
derive the best ...
MLK-16706-3 video: fbdev: mipi_dsi_northwest: add map tables for 'CM', 'CN' and 'CO'
The 'CM', 'CN' and 'CO' possible values have no apparent
relationships with their registers config values. So add
three tables to describe mappings for them.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-16706-2 video: fbdev: mipi_dsi_northwest: add 'phy_ref_clkfreq' field
Add 'phy_ref_clkfreq' field to 'struct mipi_dsi_info'
to save the reference clock frequency configed in dtb
file for mipi phy pll.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-16706-1 video: fbdev: mipi_dsi_northwest: replace 'PICOS2KHZ' by 'PICOS2KHZ2'
The 'PICOS2KHZ' macro is used to get pixel clock frequency
from 'pixclock' value to derive the required mipi phy bit
clock frequency. But the result precision get from this
macro is not good enough in some cases. The patch defines
an new improved macro 'PICOS2KHZ2' to replace 'PICOS2KHZ'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MLK-16592: arm64: dts: fsl-imx8qm-mek: Enable cs42888 codec
cs42888 can be found on i.mx8 QM MEK CPU board. It uses esai0 as a
digital audio interface.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MLK-16745-2: arm64: dts: dedicate dtb file for QM lpspi
add dedicate dtb file for lpspi nor chip on base board for i.MX8QM,
remove the CS1 pin which is not used.
BuildInfo:
- SCFW 9e9f6ec6, IMX-MKIMAGE 49a2866a, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16745-1: arm64: dts: dedicate dtb file for QXP lpspi
add a dedicate dtb file for the lpspi nor chip on base board, also
remove the unnecessary CS1 pin setting for the nor chip.
BuildInfo:
- SCFW 9e9f6ec6, IMX-MKIMAGE 49a2866a, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Signed-off-by: Han Xu <han.xu@nxp.com>
MLK-16743: Enable LVDS0 in iMX8QM arm2 and mek base device tree
Enable it6263 lvds0 in base device tree for 8QM MEK and ARM2
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
MLK-16689-03 driver: soc: Add busfreq driver for imx8mq
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:
(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.
(2): 400mts, the D...
MLK-16689-02 ARM64: dts: add busfreq node on imx8mq
Add the busfreq node used for DDR DVFS on imx8mq.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
MLK-16689-01 driver: clk: add dram_core clock on imx8mq
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
usb: dwc3: gadget: Fix ISO transfer performance
Commit 08a36b543803 ("usb: dwc3: gadget: simplify __dwc3_gadget_ep_queue()")
caused a small change in the way ISO transfer is handled in the case
when XferInProgress event happens on Isoc EP with an active transfer.
This caused a performance degradation of 50%. e.g. using g_webcam on DUT
and luvcview on host the video frame rate dropped from 16fps to 8fps
@high-speed.
Make the ISO transfer handling equivalent to that prior to that commit
to ge...
usb: dwc3: gadget: cope with XferNotReady before usb_ep_queue()
If XferNotReady comes before usb_ep_queue() we will
set our PENDING request flag and wait for a
request. However, originally, we were assuming
usb_ep_queue() would always happen before our first
XferNotReady and that causes a corner case where we
could try to issue ENDTRANSFER command before
STARTTRANSFER.
Let's fix that by tracking endpoints which have been
started.
Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com>
Si...
usb: dwc3: gadget: properly check ep cmd
The cmd argument we pass to
dwc3_send_gadget_ep_cmd() could contain extra
arguments embedded. When checking for StartTransfer
command, we need to make sure to match only lower 4
bits which contain the actual command and ignore the
rest.
Reported-by: Janusz Dziedzic <januszx.dziedzic@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
(cherry picked from commit 5999914f227b20addf01297b3df24be6b4161f69)
MLK-16716 nvmem: imx-scu-ocotp do not read invalid address
Fix: hexdump: /sys/bus/nvmem/devices/imx-ocotp0/nvmem: Input/output error
Address space [272,543] is invalid address space on 8QXP, reading from SCU
will get SC_ERR_PARAM. So ignore these words when reading fuse.
BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Signed-off-by: Peng Fan <peng.fan@nxp.com>
MLK-16726 ARM64: dts: fsl-imx8qm-lpddr4-arm2: remove lpuart0 cts/rts pin
Since lpuart0 configure as console port only, cts/rts pins are not necessary.
And lpuart2 is moved into M4 partition that will use these two pins.
So remove the two pins from dts file.
BuildInfo:
- SCFW 88456c73, IMX-MKIMAGE 06bc2767, ATF a438801
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g7953d47
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
