Commits
Shengjiu Wang committed be5e1af096f
MLK-16839-1: ASoC: fsl_asrc: selec a proper clock source from the clock list In internal ratio mode, when the clock rate can't be divided with no remainder, The final convert ratio is not as expected, there is distortion in output data. So need to select a proper clock source for this mode, if can't find a good clock source, then swith to ideal ratio mode. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>