Commits

Anson Huang committed adf1f08bdb8
ENGR00219024 [EPDC]Fix EPDC resume failure. Need to enable both axi and pix clock before doing EPDC reset, or the hardware reset will fail, which will result in dead loop of EPDC resume function, and block system resume. Signed-off-by: Anson Huang <b20788@freescale.com>