linux-wandboard

MLK-11316-3 video: mxc ipuv3 fb: Change pan display mechanism for PRE workaround

In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.

The software mechanism to set the PRE_CTRL register is different for PRE Y
resolution higher than 9 lines and lower than or equal to 9 lines.

For cases in which Y resolution is higher than 9 lines, before we update PRE
shadow, we just need to wait until the PRE store engine status runs out of
the problematic PRE automatic writing window.

While for cases in which Y resolutin is lower than or equal to 9 lines, we
have to update PRE shadow in the buffer flip interrupt handler.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit bd9c14e24aaf67926dfd31bd819ab0c87129fe4b)