Commits

Ranjani Vaidyanathan committed 9f27f73686c
ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz. When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power. Fixed warnings in dvfs_core driver. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>