Commits
Rajendra Nayak committed 7a66a39b859
omap: Lock DPLL5 at boot Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and USBTLL f-clock are the only users of this DPLL, and 120MHz is is the only recommended rate for these clocks. With this patch, the 60 MHz ULPI clock is generated correctly. Tested on an OMAP3430 SDP. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>