Commits

Zhang Jiejing committed 7191ea23fd4
ENGR00176974 MX6Q: make 624M WP work, change 624 WP to 672 WP since pll1 have a limit that cannot scaling down to 650M and below so change the 600M WP to 672MHz. otherwise, the 600WP's clock will depens on last frequency. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>