Commits
Anish Trivedi committed 6c88aca30c7
ENGR00143799 Add SCC RAM clock to dependency list for SAHARA clock tree When ARM is in WAIT mode, the SCC RAM clock is disabled since 1 is written to the CCGR register by default. At that point, if SAHARA tries to access a key or some other piece of data stored in the SCC RAM, then it might hang. To prevent this scenario, SCC RAM is added to dependency list for SCC clock, and SCC clock is added to dependency list for SAHARA. Signed-off-by: Anish Trivedi <anish@freescale.com>