linux-wandboard

MXSCM-241-2 arm: imx: coherency issues after updating lpddr2 busfreq

After a frequency transition, like 400MHz to 24Mhz, on i.mx6DQ SCM
systems (which use lpddr2), the curr_ddr_rate variable retains its
previous cached value causing the next frequency update transition
to fail by following a wrong flow which results in a complete hang
of the system.

Issuing an L1 cache flush during the freq update routine (as in in
MXSCM-241-1) and moving up the curr_ddr_rate variable before calling
tge freq update alleviates the problem.

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>