Commits
Liu Ying committed 5ae709c8472
ENGR00181194 IPUv3:Correct pixel clock definition and register MX6Q has 2 IPUs, each IPU has 2 DIs, so there are totally 4 different pixel clocks. This patch adds maximal pixel clock number from 2 to 4. Also, the patch fixes potential build warning caused by the overflow on ipu_lookups structure in case MXC_IPU_MAX_NUM is 1. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>