Commits
Anson Huang committed 4bc54b1515b
ENGR00174974 [MX6]Fix CPU hotplug platform related issue We need to turn of cache coherency of secondary core before it is disable by core0, otherwise, the secondary core may be waked by cache sync, and if it exit from wfi and access BUS, meanwhile, core0 disable it from hardware, the whole SOC would hang. Signed-off-by: Anson Huang <b20788@freescale.com>