Commits
Shengjiu Wang committed 48293e6bf77
MLK-12722: ASoC: fsl_spdif: clear the validity bit for TX Validity bit is set in default, which means the data is not reliable, The receive device may drop this data. So clear it in default, and provide a mixer interface for user to control this bit. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>