Commits
Jisheng Zhang committed 44991eb4bfd
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>