linux-wandboard

MLK-13507 ARM: imx: workaround of ERR010579 for ipu on imx6dl

Workaround for ERR010579
When switching the clock  source of IPU clock root in CCM, even setting
CCGR3[CG0]=0x0 to gate off clock before switching, IPU may hang due to
no IPU clock from CCM. The root cause is an integration bug in SOC level,
setting CCGR3[CG0]=0x0 can NOT gate off the clock after IPU clock source MUX.

The IPU clock source MUX is glitchg MUX, that means the clock glitch during
clock switch is unavoidable, which will cause the divider after it stop work
and no clock output. In order to avoid the clock glitch, we must obey below
procedures if clock source switch is needed:

1. gate off the CG after MUX
2. switch clock source
3. gate on the CG after MUX

On the other hand, the EN of the CG between MUX and divider is a feedback
logic(OR result) from several LPCG cells in SOC top, but for IPU clock, one
LPCG is forced to open forever, then the feedback OR result is always high,
it causes the CG can NOT be gated off even the CCGR3[CG0] is set to 0x0.

For detailed workaround steps, please refer to the errata document.

Tested-by: Ying Liu <victor.liu@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>