Commits
Richard Zhu committed 1e9813c6c48
ENGR00174315 MX6Q max7310 set the default value of PCIE PWR ctrl2 to low System would be halt, when the default value CTRL_2 is set to high, change the default value to low. root cause: System 3V3 would be dragged down to 1.5V for about 4ms. Signed-off-by: Richard Zhu <r65037@freescale.com>