linux-wandboard

MLK-11484-5 pci: imx: enable pcie ep rc system on imx7d

Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platforms

hw setup:
* two imx boards, one is used as pcie rc, the other is used
as pcie ep. Connected by fsl pcie adap adaptor.

sw setup:
* when build rc image, make sure that
  CONFIG_IMX_PCIE=y
  # CONFIG_EP_MODE_IN_EP_RC_SYS is not set
  CONFIG_RC_MODE_IN_EP_RC_SYS=y
* when build ep image
  CONFIG_IMX_PCIE=y
  CONFIG_EP_MODE_IN_EP_RC_SYS=y
  # CONFIG_RC_MODE_IN_EP_RC_SYS is not set

features:
* set-up link between rc and ep by their stand-alone
ref clk running internally.

* in ep's system, ep can access the reserved ddr memory
(default address:0x4000_0000 on imx6q sd board, and
0xb000_0000 on imx6sx sdb and imx7d arm2 boards) of
pcie rc's system, by the interconnection between pcie
ep and pcie rc.

* add the configuration methods in the ep side, used to
configure the start address and the size of the reserved
rc's memory window.
  - cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
  - echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
  - echo 0x200000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set

* provide one example, howto configure the bar# and so on,
when pcie ep emaluates one memory ram ep device

* setup one new outbound memory region at rc side, used
to let imx pcie rc can access the memory of imx pcie ep
in imx pcie rc ep validation system.
  - set the default address of the ddr memory to be 0x4000_0000
  on imxq sd board, and 0xb000_0000 on imx6sx sdb and imx7d
  arm2 boards.

NOTE:
* boot up ep platform firstly, then boot up rc platform.
* make sure that mem=768M is contained in the kernel command line,
since the start address of the upper 256mb of the 1g ddr mem is
reserved to do the pcie ep rc access operations in default.

Test howto of the RC access memory of EP on imx6q sd platforms.
step1:
EP side:
1.1:
echo <768M_DDR_MEM_ADDR> > /sys/devices/.../pcie/ep_bar0_addr

1.2:
memtool -32 <768M_DDR_MEM_ADDR> 4
E
Reading 0x4 count starting at address 0x40000000

<768M_DDR_MEM_ADDR>:  6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78

step2:
RC side:
memtool -32 <PCI_BASE_ADDR> =58D454DA
memtool -32 <PCI_BASE_ADDR + 4> =7332095B

step3:
EP side:
memtool -32 <768M_DDR_MEM_ADDR> 4
E
Reading 0x4 count starting at address 0x40000000

<768M_DDR_MEM_ADDR>:  58D454DA 7332095B 39EAEFEA FBDCFD78

Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>