Commits
Anson Huang committed 00f4dad1eaf
ENGR00267442 mx6: clk: some clock settings are incorrect 1. The ipg_per clock rate setting should be done after its parent initilization done, otherwise it will get wrong parent rate and lead to incorrect rate setting; 2. The parent info of emi_clk has been changed in latest RM, need to update it according to RM, the parent info is as below: 2b'00: 396M PFD; 2b'01: PLL3; 2b'10: AXI; 2b'11: 352M PFD. Signed-off-by: Anson Huang <b20788@freescale.com>