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AuthorCommitMessageCommit Date
Shengjiu WangShengjiu Wang
ea705346437MLK-16350-4: ASoC: imx_mqs: fix the clock rate issue The rate returned by clk_get_rate in probe function is not correct, for the power domain in that time may be closed, kernel get 0 rate from scfw, so move the clk_get_rate to hw_params, in that time, the power domain should be enabled Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu WangShengjiu Wang
7adbe0a4c99MLK-16350-3: ASoC: imx-cs42888: fix clock rate issue The rate returned by clk_get_rate in probe function is not correct, for the power domain in that time may be closed, kernel get 0 rate from scfw, so move the clk_get_rate to hw_params, in that time, the power domain should be enabled Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu WangShengjiu Wang
e006cd8fce2MLK-16350-2: ASoC: fsl_mqs: enable the pm_runtime enable the pm_runtime, the power domains wil be disabled when mqs is idle. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu WangShengjiu Wang
f3776ecfa53MLK-16350-1: ARM64: dts: add the clocks for each node In current design, the assigned-clock-rates is bind with each device node, even they are using same parent clocks. so add clocks for each device. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Meng MingmingMeng Mingming
1717142276bMLK-15321-4 drm/imx: core: Add bliteng as component of imx-drm Implement Blt engine as DRM renderer. Add dpu bliteng as component of imx-drm. Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com> Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
f2ebd5dd309MLK-15321-3 drm/imx: dpu: Add render feature support Implement Blt engine as DRM renderer. Add dpu ioctl to support imx-drm render feature. Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com> Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com> Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
9c0dd958b0cMLK-15321-2 gpu: imx: dpu: Add dpu blit engine driver Implement Blt engine as DRM renderer. Add dpu blit engine driver. Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
0fdb422beefMLK-15321-1 gpu: imx: dpu: Add dpu blit engine device Implement Blt engine as DRM renderer. Add dpu blit engine device. And as dpu bliteng has no device tree node, so to set dpu's of_node as the platform data for imx-drm component compare_of. Signed-off-by: Meng Mingming <mingming.meng@nxp.com> Acked-by: Liu Ying <victor.liu@nxp.com>
Richard ZhuRichard Zhu
8c2a5e4dd7fMLK-16345 PCI: imx: final workaround of ERR010728 for pcie Description: Initial VCO oscillation may fail under corner conditions such as cold temperature. It causes PCIe PLL fail to lock in initialization phase. Project Impact: iMX7D PCIe PLL fails to lock and PCIe doesn.t work. workarounds: To disable Duty-cycle Corrector(DCC) calibration after G_RST signal is de-asserted by following the sequences: 1. De-assert the G_RST signal by clearing SRC_PCIEPHY_RCR[PCIEPHY_G_RST]. 2. de-a...
Shengjiu WangShengjiu Wang
fee214c0fb3MLK-16257: soc: imx: fix clock rate store issue in power off In the case assign same clock in two device node in dts, which is a parent clock used by two devices. In current design, we need to assign this clock in two device node for clock rate recovery. In this case, clock rate getted in imx8_pd_power_off() is zero for second device, which will cause the clock recovery failed. The calling sequence like this: First device probe: --> of_clk_set_defaults --> clk_set_rate --> clk_cor...
Anson HuangAnson Huang
f24986e50d1MLK-16351 rtc: imx-sc: use SIP to set RTC time For system controller RTC, as it belongs SC_R_SYSTEM, and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware, so here needs to use SIP to trap into ATF to do set time, or system controller firmware will return error since linux kernel does NOT own this system resource. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
XianzhongXianzhong
d0f93fbf84fMGS-3251 [#imx-701] fix power-off issue for ctrl-C exit there are lots of events to pipeline for database destroy, wait for event queue empty before do power-off for last process. side note for the proposed solution: it is not the way to flush pipeline in drv_release thread, since the clock may be turned off by other threads unexpectedly, also the potential deadlock if lock up the power in drv_release. Date: Aug 31, 2017 Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Yuchou GanYuchou Gan
ad0d7366045MGS-3177 [#imx-701] fix the wrong FPS issue on DRM wayland The former patch "Fix power-off random failure when GPU become idle" which wait for gpu idle when tried to power off that will cause performance drops when multi applications run at the same time. Refine this patch so that the patch only run at first time when probe, suspend or last process run finished. Date: Aug 29, 2017 Signed-off-by: Yuchou Gan yuchou.gan@nxp.com
Fancy FangFancy Fang
6865dc5d557MLK-16349 video: fbdev: dcss: reset dcss domains before clock source config Before accssing any DCSS register, add the DCSS domains reset before DCSS clock source configuration, since DCSS clock source configuration requires all the DCSS domains to be in reset state according to the DCSS specification. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Guoniu.ZhouGuoniu.Zhou
db00aa2b138MLK-16348: PxP: fix background issue There was no pxp background register setting, so the background we see always black. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit d3ee45e2671478854a165f34f91fabac247e8a39)
Li JunLi Jun
1547c79294aMLK-16298-2 ARM64: imx8mq-evk: typec super speed mux select gpio update Use GPIO_ACTIVE_HIGH for super speed signal mux selection GPIO as we should pull it up to be high for CC1 according to PTN36043. Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
Li JunLi Jun
c895d15bd04MLK-16298-1 staging: typec: make super speed signal mux select configurable Instead of fixed pull up super speed mux selection gpio for cc1, use GPIO_ACTIVE_HIGH/LOW to map the CC1/CC2 orientation via gpiod api, So for ss-sel-gpios: GPIO_ACTIVE_HIGH: CC1 <--> GPIO high GPIO_ACTIVE_LOW : CC1 <--> GPIO low Acked-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
Guoniu.ZhouGuoniu.Zhou
95b732f5376MMFMWK-7674: PxP: add YVU420P support PxP PS engine support YUV420 format, but not YVU420. The difference between two format is U and V, if we exchange U and V base address, the PxP driver can also support YVU420 format. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit cbc71da10afe67ae815a97a68e4a1b0dff4693eb)
Liu YingLiu Ying
8c5c76769b9MLK-16290 drm: Add drm_of_component_probe_with_match() helper A component master may have both OF based and non-OF based components to be bound with. This patch adds a helper drm_of_component_probe_with_match() similar to drm_of_component_probe() so that the new helper may get an additional provided match pointer(contains match entries for non-OF based components) to support this case. Tested-by: Meng Mingming <mingming.meng@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
5baa582cd51MLK-16301-2 gpu: imx: dpu: common: Remove the list in dpu plane group No one is using the list in the dpu plane group, so let's remove it and the mutex lock which protects the list. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Liu YingLiu Ying
dcd85a5915bMLK-16301-1 drm/imx: dpu: plane: Take down dpu plane from the dpu plane grp list No one is using the list in the dpu plane group to access dpu plane, so let's take down dpu plane from the list so that we may remove the list entirely from where it is defined. Signed-off-by: Liu Ying <victor.liu@nxp.com>
Han XuHan Xu
050b5175a9bMLK-16331: arm64: dts: enable flexspi on i.MX8QXP MEK enable flexspi on i.MX8QXP MEK Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
ead7484e08bMLK-16330: mtd: fsl-quadspi: remove unnecessary variable Remove the unnecessary tmp array from code Signed-off-by: Han Xu <han.xu@nxp.com>
Han XuHan Xu
c967ff22cbaMLK-16329-2: mtd: fsl-flexspi: fix the start address alignment issue FLEXSPI AHBCR register has one bit READADDROPT, which defined if start address must be aligned when doing wordaddress access. This bit must be set (no alignment limitation), otherwise controller may always try to access from even address and got wrong data when AHB read data under Octal DDR mode. Mounting UBIFS failed in this case since it read from odd address. [ 250.367893] fsl_fspi_read: from 620ad1, len: 11 [ 250.374...
Han XuHan Xu
dc9a7058c44MLK-16329-1: mtd: fsl-flexspi: fix the unalignment issue for fspi ARM64 platforms may access FSPI from non-64-bit-aligned address which causes unalignment fault. Fixed the issue for AHB reading. Signed-off-by: Han Xu <han.xu@nxp.com>
Ranjani VaidyanathanRanjani Vaidyanathan
d71aacee264MLK-16264 soc:imx8qm/imx8qxp: Update to the latest SCFW API Update uboot to the latest SCFW based on commit: " commit 129c16e312334af7b07d71d6dccac1cda1808b93 Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Date: Thu Aug 24 16:50:59 2017 -0500 Add support to change DRC clock rate. " Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Adriana ReusAdriana Reus
278b5fc78acMLK-16281-2: clk-imx8qm: Fix GPT clock hierarchy There are five gpt modules on imx8qm (gpt0 .. gpt4). Of these, gpt2 and gpt4 clock hierarchies are inconsistent with the rest. Having the per clocks (gpt_hf_clk and gpt_clk) as children of the peripheral access clock (ipg_s) and bus sync slave clock (ipg_slv_clk) ensures that the latter are enabled when the driver enables the gpt_clk (or hf). This patch reconciles these two gpt clock trees with the rest. Before: gpt_2_div gpt_2_hf_clk ...
Adriana ReusAdriana Reus
ed8ec487917MLK-16281-1: clk-imx8qm: Remove duplicated gpt clocks Some gpt clocks are defined twice which results in: gpt0_div gpt0_clk and also: gpt_0_div gpt_0_ipg_s_clk gpt_0_ipg_slv_clk gpt_0_hf_clk gpt_0_clk The second version is correct as per gpt lpcg cell. This patch removes the first set of clocks. Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Guoniu.ZhouGuoniu.Zhou
aac1fbdd406MLK-16276: PxP: Improve code compatibility g2d code has different parameter setting about stride parameter. For compatibility with all cases of using PxP, we need add this improved feature. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit 53c8ffffec181a765f4487a9d1bf2eb05b1b78f7)
Guoniu.ZhouGuoniu.Zhou
8c42c6e1ee7MLK-16252: PxP: fix video shift issue If pxp use crop x/y valuse as the upper left coordinate in out buffer, pxp driver only need to write out buffer base address to pxp out_buf register. If pxp driver use zero as ps_ulc register value, pxp out_buf register need an offset added with out buffer base address. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit 14c988f1eb7e9471b087501...
Viorel SumanViorel Suman
c629a9205a6MLK-16275: ARM64: dts: imx8qxp-mek: Enable AMIX Enable AMIX support and fix the clock tree rates for IMX8QXP_AUD_MCLKOUT0. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Anson HuangAnson Huang
118352fbdaeMLK-16300 thermal: imx: avoid error message of get_temp when thermal zone is off For i.MX system controller thermal, when some of the thermal zones are powered off, the get temp will fail, and thermal driver will return CPU thermal zone's temp instead. But current driver will return A53 cluster for all cases, and A53 cluster may be also off when booting up A72 cluster only, so below error message will come out: [ 475.606431] read temp sensor:0 failed [ 475.610107] thermal thermal_zone0: f...
Anson HuangAnson Huang
2f307b49fe9MLK-16286-2 defconfig: enable cpu-freq schedutil governor Enable cpu-freq schedutil governor by default. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
Anson HuangAnson Huang
38650963723MLK-16286-1 arm64: dts: freescale: imx8qm: add cpu opp table Add i.MX8QM CPU OPP table to support cpu-freq. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
Meng MingmingMeng Mingming
e8c3fcff5a4MLK-16291-4: Revert "MLK-15321 dpu-blit: Add dpu blit engine driver" This reverts commit 60fd1ffd2873 ("MLK-15321 dpu-blit: Add dpu blit engine driver"). Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
8e483cad2ceMLK-16291-3: Revert "MLK-15321 dpu: Register the blit engine(s)." This reverts commit 9b9d4d8ab1ec ("MLK-15321 dpu: Register the blit engine(s)."). It's no need to add dpu_add_feature_devices(), and it's better to identify bliteng as a device but a feature. Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
27850fdbb72MLK-16291-2: Revert "MLK-15321 drm,imx: Add DRM support for dpu-blit" This reverts commit b4c70b278a5e ("MLK-15321 drm,imx: Add DRM support for dpu-blit"). It's no need to invent register/unregister solution to add dpu bliteng ioctl. It's complex and overengineering. And currently we will choose a simple way as drm->driver->ioctls = imx_drm_dpu_ioctls. Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Meng MingmingMeng Mingming
2fc5de08f0eMLK-16291-1: Revert "MGS-3800 drm,imx: drop drm_of_component_probe() in favor of imx specifics." This reverts commit 97ca244f0470 ("MGS-3800 drm,imx: drop drm_of_component_probe() in favor of imx specifics."). It need remove add_display_components() and add a new method as drm_of_component_probe_with_match(). Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
Haibo ChenHaibo Chen
1ce1f3c2947MLK-16274 ARM64: dts: correct the pad setting of USDHC i.MX8QM/i.MX8QX USDHC pads are dual voltage pads, and the defiintation of each bit are different. Only bit[0] define the drive strength slection, bit[4:1] are reserved. 0 means high drive strength 1 means low drive strength This patch correct these pad setting, setting the usdhc 100mhz/200mhz pin at high drive strength. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Haibo ChenHaibo Chen
fdeb9f9e1c2MLK-16155-13 mmc: sdhci-esdhc-imx: add DCMD support for CMDQ Currently, USDHC do not generate transfer complete interrupt when send a non-data-command with R1b response. But if want to support DCMD in CMDQ, need to change this, the DCMD IC logic require the USDHC to enable this function, otherwise DCMD will never get a CC(command complete) interrupt. This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Dong Aisheng <a...
Haibo ChenHaibo Chen
9fa76e7bc3fMLK-16155-12 mmc: sdhci-esdhc-imx: add CMDQ support Add CMDQ support for imx8qm/imx8qxp. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Haibo ChenHaibo Chen
e58f177e0a3MLK-16155-11 mmc: sdhci: correct the maximum timeout when enable CMDQ Priority use the callback set_timeout() to set the maximum timeout if the host has. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Venkat GopalakrishnanVenkat Gopalakrishnan
d61c17f44ffMLK-16155-10 mmc: cqhci: support for command queue enabled host This patch adds CMDQ support for command-queue compatible hosts. Command queue is added in eMMC-5.1 specification. This enables the controller to process upto 32 requests at a time. Adrian Hunter contributed renaming to cqhci, recovery, suspend and resume, cqhci_off, cqhci_wait_for_idle, and external timeout handling. Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.or...
Adrian HunterAdrian Hunter
49132bb305dMLK-16155-9 mmc: block: Add CQE support Add CQE support to the block driver, including: - optionally using DCMD for flush requests - manually issuing discard requests - issuing read / write requests to the CQE - supporting block-layer timeouts - handling recovery - supporting re-tuning Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
dbf3d0e9a60MLK-16155-8 mmc: block: Prepare CQE data Enhance mmc_blk_data_prep() to support CQE requests. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
0f6b250a271MLK-16155-7 mmc: mmc: Enable CQE's Enable or disable CQE when a card is added or removed respectively. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
c42ed0f9e77MLK-16155-6 mmc: mmc: Enable Command Queuing Enable the Command Queue if the host controller supports i a command queue engine. It is not compatible with Packed Commands, so do not enable that at the same time. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
60ca947db0aMLK-16155-5 mmc: core: Add support for handling CQE requests Add core support for handling CQE requests, including starting, completing and recovering. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
93d8a32fbe7MLK-16155-4 mmc: core: Turn off CQE before sending commands Turn off the CQE before sending commands, and ensure it is off in any reset or power management paths, or re-tuning. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Adrian HunterAdrian Hunter
9043e1ebe63MLK-16155-3 mmc: host: Add CQE interface Add CQE host operations, capabilities, and host members. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com>